Estimation Method Considering OS Overheads for Embedded Many-Core Platform

This paper explores and evaluates the potential of deep neural network (DNN)-based machine learning algorithms on embed-ded many-core processors in cyber-physical systems, such as self-driving systems. To run applications in embedded systems, a plat-form characterized by low power consumption with high accuracy and real-time performance is required. Furthermore, a platform is required that allows the coexistence of DNN applications and other applications, including conventional real-time control soft-ware, to enable advanced embedded systems, such as self-driving systems. Clustered many-core processors, such as Kalray MPPA3-80 Coolidge, can run multiple applications on a single platform because each cluster can run applications independently. Moreover, MPPA3-80 integrates multiple arithmetic elements that operate at low frequencies, thereby enabling high performance and low power consumption comparable to that of embedded graphics processing units. Furthermore, the Kalray Neural Network (KaNN) code generator, a deep learning inference compiler for the MPPA3-80 platform, can efficiently perform DNN inference on MPPA3-80. This paper evaluates DNN models, including You Only Look Once (YOLO)-based and Single Shot MultiBox Detector (SSD)-based mod-els, on MPPA3-80. The evaluation examines the frame rate and power consumption in relation to the size of the input image, the computational accuracy, and the number of clusters.

As a standard of operating system in automotive industry, OSEK/VDX is applied on dozens of mature industrial operating systems and widely installed on the products of major automotive manufacturers. In this empirical report, we introduce our experience on verifying OSEK/VDX real-time operating system. From both source code and binary code level, the OSEK/VDX operating system is verified based on approaches comprising Hoare Logic, Communicating Sequential Processes, Binary Code Analysis and Discrete-Time Markov Chains model checking. Based on our approach, a commercial OSEK/VDX standard automotive operating system is verified and it is proved to be of great help to the development of software.

The complexity of consumer electronics devices have them employ more powerful processors as their processing load becomes higher; thus, their higher power consumption becomes a critical problem. In order to balance processing power and electrical power consumption, heterogeneous multi-core processors are becoming popular. This paper proposes an extensible RTOS (real-time operating system) architecture for such heterogeneous multi-core processors, which consist of processors with different processing power and functionalities. The architecture splits the RTOS kernel into the two components, the proxy kernel (PK) and user-level kernel (UK), and decouples dynamic resource management functions from the PK. Such architecture enables the PK to run on a less powerful core while RTOS can utilize dynamic resource management functions provided by the UK. The experiment results running micro benchmark programs show the feasibility of the proposed architecture.

Millimeter wave(mmWave) supported Massive MIMO systems with directional beamforming enables gigabit-per-second data rates with large bandwidth and achieves sufficient link margin but algorithms, system operations still rely on microwave-based modifications. The mmWave channel has a very poor scattering nature, so sensing channel parameters need very large training pilot signals. The Presence of large antenna arrays with analog beamforming and giga-sample mixed-signal devices cause computational complexities and high power consumption. Realizing these issues, we propose a mmWave specific deep-learning enabled adaptive-compressive based channel sensing and hybrid beamforming solution that jointly optimizes the channel vectors in an unsupervised manner and generate RF beamforming/combining vectors that achieve precoding gains comparable to near-optimal achievable rates. Simulation results show that for a 64 by 64 transmit-receive antenna system, existing exhaustive search algorithm needs 4096 channel pilot signals, compressive algorithms need minimum 300 pilots. In contrast, our proposed solution needs only 4 pilots to sense the channel parameters and directly predicts RF beamforming/combining vectors for the hybrid architectures. Lesser channel training pilots cause low power consumption and proposed hybrid RF precoding solution overcomes hardware limitations faced by analog-only beamforming that shows up a promising development for the solution of mmwave channel estimation and hybrid precoding problem.

In precision agriculture technology system, cropland data acquisition acts as the foundation as well as the weakness of our countrypsilas research on this field. In this dissertation, according to the present actual demands, an embedded cropland data acquisition and processing system is designed. The system is supposed to achieve many tasks such as agricultural sensors data acquisition, GPS information acquisition and navigation. During the process of design, factors such as performance, cost, and expansibility are all taken into account. The hardware is based on a 32-bit embedded microprocessor with high performance but low power consumption - Intel Xscale PXA270, while the real-time operating system is Windows CE 5.0. This design has very important practical significance to speed up the process of agricultural modernization in China.

The core idea in this project is to have two operating systems for both cores of dual core processor individually. General purpose operating system on one core and Real time operating system (RTOS) on second core. Implementation of same will be done by making one of core independent from General purpose operating system and install RTOS in that core so that both will work as one system i.e. General purpose operating system will look after the non-real time applications and RTOS will ensure that all real time application should not miss their deadline and executed as fast as they can. As by installing general purpose operating system and RTOS in both the cores of dual core processors of system and running them in parallel way, dual core processors is being used to its maximum efficiency. The advantage is that if one of OS gets crashed, whole system will not crash instead one of OS which didn't crash hold the system to safe mode till damaged OS is recovered.

This paper discuss on how to develop a hard real-time machine control system with Microsoft Windows NT Operating System, where the respond must be within 0.5 milliseconds. The attempt to use a general-purpose operating system (Microsoft Windows NT 4.0 Workstation) is because there is abundance of Commercial-Off-the-Shelf Components (COTS), easily available tools (compilers, and 3 party tools) and need not to learn another operating system behavior. The most important factor is there is no single dominant operating system or tools vendor for real-time operating system. Since the no single dominant real-time operating system development under real-time operating system is riskier and more costly. Ideally codes must be portable between different operating system where it is apparent with Windows platforms, Windows 95/98, Windows ME, Windows 2000, Windows XP or even Windows CE. Firstly study was done on how Microsoft Windows NT operating system works internally from materials from Microsoft Software Development Network (MSDN). Secondly study was done how to take advantage of the operating system to create a real time application. Microsoft Windows NT is a general purpose operating system that does not support real time application development, but it has all the vital elements that a real time operating system needs. The vital elements are priority-driven, preemptive scheduler, preemptive interrupt handler (for critical interrupts), deferred procedure calls (DPC) for non-critical (DPC executes after ISR), synchronization and deterministic response time. With these vital elements and some modification to application codes to enable it to execute in higher priority level, would result a real time application. This does not mean changing all the codes to higher priority is the solution, as it would cause system to malfunction as other device driver or low-level interface run at high priority too and this would lock up the system. With the combination of priority level, synchronization a complete real time solution can be implemented and this paper covers the concept. This concept also explains what was done to overcome the need of special hardware (as recommended) to accomplish hard real-time application with the response of 0.5 milliseconds.

Efficiency of Network-on-Chip based many-core microprocessors to implement parallel fault simulation methods for different circuit sizes is explored in this paper. We show that a naive and straightforward execution of fault simulation programs on such systems does not provide the maximum speedup due to severe bottlenecks in off-chip shared memory access at memory controllers. In order to exploit the available massive parallelism of homogenous many-core microprocessors, a runtime approach capable of adaptively balancing the load during the fault simulation process is proposed. We demonstrate the proposed adaptive fault simulation approach on a many-core platform, Intels Single-chip Cloud Computer showing up to 45X speedup compared to a serial fault simulation approach.

System design kit for the 8051

Real-time Linux operating system for plasma control on FTU—implementation advantages and first experimental results

On the energy efficiency and performance of irregular application executions on multicore, NUMA and manycore platforms

This paper presents the basics of an operating systems plus RTOS(Real Time Operating System) specific features. Readers are expected to have an overview of the foundations of embedded operating systems and especially RTOS. Operating systems have been evaluated by different commercial and non profit organizations. It can be seen the main lines of different operating systems.

Silicon photonics have emerged as a promising solution to meet the growing demand for high-bandwidth, low-latency, and energy-efficient on-chip and off-chip communication in many-core processors. However, current silicon-photonic interconnect designs for many-core processors waste a significant amount of power because (a) lasers are always on, even during periods of interconnect inactivity, and (b) microring resonators employ heaters which consume a significant amount of power just to overcome thermal variations and maintain communication on the photonic links, especially in a 3D-stacked design. The problem of high laser power consumption is particularly important as lasers typically have very low energy efficiency, and photonic interconnects often remain underutilized both in scientific computing (compute-intensive execution phases underutilize the interconnect), and in server computing (servers in Google-scale datacenters have a typical utilization of less than 30%). We address the high laser power consumption by proposing EcoLaser+, which is a laser control scheme that saves energy by predicting the interconnect activity and opportunistically turning the on-chip laser off when possible, and also by scaling the width of the communication link based on a runtime prediction of the expected message length. Our laser control scheme can save up to 62 - 92% of the laser energy, and improve the energy efficiency of a manycore processor with negligible performance penalty. We address the high trimming (heating) power consumption of the microrings by proposing insulation methods that reduce the impact of localized heating induced by highly-active components on the 3D-stacked logic die.

The semiconductor industry has enjoyed unprecedented growth over the last two decades fueled by the PC/internet era (2000s) and the Mobile/Social Media era (2010s). We are now entering the Artificial Intelligence/Big Data era which is predicted to push the industry towards $1T in revenue by the early 2030s1. AI applications require massive amounts of computational power and power consumption. To keep pace with expected computational demands and ensure that the industry does not put strain on the global power supply, device makers are looking at ways to increase compute while driving lower operational power consumption. The image below showcases TSMC’s device architecture roadmap on new transistor architectures and gives insight into a path on new integrated materials2. After gate-all-around nanosheets (entering trial production today), TSMC will enter the 3D regime with transistor stacking called CFETs (complementary field-effect transistors). 3D integration of devices is a common strategy across the industry from logic to memory to continue scaling trends. Stacking the devices is shown to increase performance, decrease area cost, and decrease power consumption. Realization of these complex architectures requires very stringent and rigorous fabrication steps with various patterning techniques and new processes. Selective deposition has been identified as one primary method to simplify integration schemes to lower complexity and cost. For example, selective deposition can mitigate issues encountered in fine pitch lithography such as edge placement error that can lead to reliability and performance issues like BEOL contact shorts. Applied Materials is the current leader in selective deposition processing, and we have fielded multiple products that are being used to fabricate cutting-edge devices at leading edge customers. This discussion will focus on the trials and tribulations of ASD, and how it is enabling our customers to reduce power consumption while increasing performance all at a lower area cost, which will be crucial to the future sustainability of this industry.1. https://www.semi.org/en/blogs/semi-news/global-semiconductor-industry-driving-%241-trillion-and-beyond-together2. TSMC 2023 North America Technology Symposium (April 26th, 2023) Figure 1

We present a hardware/software RTOS (real-time operating systems) generation framework for system-on-a-chip (SoC) applications. We claim that current SoC designs tend to ignore the RTOS until late in the SoC design phase. In contrast, we propose RTOS/SoC codesign where both the multiprocessor SoC architecture and a custom RTOS (with part potentially in hardware) are designed together. Thus, this paper introduces a hardware/software RTOS generation framework for customized design of an RTOS within specific predefined RTOS services and capabilities available in software and/or hardware (depending on the service or capability).