Evaluating impact on CMPs' power for design inaccuracy diagnosis

Purpose. To obtain analytical dependencies for the precise calculation of the stator current of a frequency-regulated three-phase short-circuited induction motor and to estimate the components of its main electrical power losses, which are spent on the transportation magnetic power losses (to the magnetization circuit) and additional power losses (through the motor air gap), as well as with using the obtained refined dependencies to research the electromagnetic processes and energy modes of the frequency-regulated induction motor when its speed and load change. Methodology. The method of generalized vectors is used for the refined calculation of the electromagnetic processes and energy modes of the frequency-regulated induction motor. Results. Based on the catalog data and parameters of the induction motor’s equivalent replacement circuit, also the specified values of its useful rotational torque and speed, refined analytical dependencies were obtained for the calculation of the main electromagnetic power losses of the frequency-regulated induction motor, which take into account the influence of all types of power losses, which present in it, as well as – power losses spent on transporting magnetic losses (to the magnetization circuit) and additional losses (through the air gap of the motor). With the help of the obtained dependencies, the energy modes (including main power consumption and electromagnetic power losses, efficiency factor, power factor) of the frequency-regulated induction motor in the driving and generator modes of its operation in relation to the first (at speeds not higher than the nominal) and the second (at speeds above the nominal) speed control zones for the operating ranges of the motor useful rotational torque and speed changes were calculated. Originality. A refined analytical calculation dependence has been obtained for determining the active projection of the generalized stator current vector of a frequency-regulated induction motor, which takes into account the presence of additional power losses and the component of electrical losses caused by the transportation of additional power losses through the air gap of the motor; an analytical dependence is also proposed for determining the increment of the mentioned active projection, which is due to the transportation of magnetic power losses to the motor magnetization circuit. Practical value. Analytical calculation dependencies are proposed for the quantitative assessment of errors (as a percentage of mentioned values) in steady-state modes for determining the main electromagnetic power losses of the frequency-regulated induction motor, caused by the absence (in comparison with relevant studies from known publications) of taking into account additional and magnetic power losses, as well as – the influence of electrical component losses caused by the transportation of the mentioned power losses through the air gap or to the magnetization circuit of the motor, respectively. References 16, tables 5, figures 2.

Inter-thread or intra-thread interference misses may be incurred due to the conflict among different threads when the least-recently-used (LRU) victim candidate is evicted from the shared last level cache in Chip Multiprocessors (CMP). To alleviate this problem, an interference miss isolation mechanism based on skewed mapping (IMI-SM) is proposed for the shared cache in this paper, which is aimed to mitigate the conflict miss phenomena when the on-chip cache is occupied competitively by multiple threads in CMP. The skewed mapping mechanism in IMI-SM is triggered once an interference miss is predicted. The new incoming data fetched from the off-chip memory can be dynamically placed in an dedicated isolation cache or the cache set which is under light pressure, so the negative impact caused by the interference misses in the shared cache is mitigated effectively. Experimental results based on full system simulator demonstrate that IMI-SM can reduce the interference misses in the shared last level cache to a certain extent, and the system performance is improved significantly with negligible hardware overhead.

Most of today's chip multiprocessors implement last-level shared caches as non-uniform cache architectures. A major problem faced by such multicore architectures is cache line placement, especially in scenarios where multiple cores compete for line usage in the single non-uniform shared L2 cache. Block migration has been suggested to overcome the problem of optimum placement of cache blocks. Previous research, however, shows that an uncontrolled block migration scheme leads to scenarios where a cache line `ping-pongs' between two requesting cores resulting in higher access latency for both the requestors and greater power dissipation. To address this problem, this paper first proposes a mechanism to dynamically profile data block usage from different cores on the chip. We then propose an adaptive migration---replication scheme for shared last-level non-uniform cache architectures that adapts between selectively replicating frequently used cache lines near the requesting cores and cache line migration towards the requesting core in case of fewer requests. AMR eliminates `ping-ponging' of cache lines between the banks of the requesting cores. However, any mechanism that dynamically adapts between migration and replication at runtime is bound to have a complex search scheme to locate data blocks. To simplify the data lookup policy, this work also presents an efficient data access mechanism for non-uniform cache architectures. Our proposal relies on low overhead and highly accurate in-hardware pointers to keep track of the on-chip location of the cache block. We show that our proposed scheme reduces the completion time by on average 12.25, 8.1 and 3 % and energy consumption by 11.65, 8.5 and 2.1 % when compared to state-of-the-art last-level cache management schemes S-NUCA, D-NUCA and HK-NUCA, respectively. SPEC and PARSEC benchmarks were used to thoroughly evaluate our proposal.

With continuous technology scaling, current and next generation microprocessors are becoming more vulnerable to transient errors such as soft errors induced by energetic particle strikes. While mainstream microprocessors are employing multi-/many-core architectures targeting at high-performance parallel computing applications, the transistor/area share of on-chip caches keeps increasing. As cache memories being the major victim of soft errors, it is of paramount importance to characterize on-chip cache's vulnerability in this context for devising potential reliability optimizations, especially under the interaction with cache coherence protocols. In this work, we develop a lifetime model for the private L1 data cache in chip-multiprocessors (CMPs), which is based on the cache activities and the states of cache lines. This lifetime model is then applied to characterize and predict cache's vulnerability trend in CMPs. Our experimental evaluation shows that cache vulnerable phases due to remote accesses increase dramatically as the number of processor cores increases. Based on vulnerable phase analysis, we propose a protocol enhancement to prematurely invalidate cache lines in modified (M) state for minimizing the vulnerability factor due to remote reads to modified cachelines.

Exploring the vast microarchitectural design space of chip multiprocessors (CMPs) through the traditional approach of exhaustive simulations is impractical due to the long simulation times and its super-linear increase with core scaling. Kernel based statistical machine learning algorithms can potentially help predict multiple performance metrics with non-linear dependence on the CMP design parameters. In this paper, we describe and evaluate a machine learning framework that uses Kernel Canonical Correlation Analysis (KCCA) to predict the power dissipation and performance of CMPs. Specifically we focus on modeling the microarchitecture of a highly multithreaded CMP targeted towards packet processing. We use a cycle accurate CMP simulator to generate training samples required to build the model. Despite sampling only 0.016% of the design space we observe a median error of 6-10% in the KCCA predicted processor power dissipation and performance.

This work reports a high speed protocol verificaion logic for Chip Multiprocessors (CMPs) realizing directory based cache coherence system. A special class of cellular automata (CA) referred to as single length cycle 2-attractor CA (TACA), has been introduced to identify the inconsistencies in cache line states of processors private caches. The introduction of CA segmentation logic ensures a better efficiency in the design by reducing the number of computation steps of the verification logic by a factor of the number of segments. The cache coherence verification for a system with limited directory has also been addressed. The TACA keeps trace of the coherence status of the CMPs' cache system and memorizes any inconsistent recording done during the processors' reference. Theory has been developed to realize quick decision on the cache coherency.

Network-on-Chip (NoC) has been a viable solution for resolving the complexities associated with inter-processor communications in a Chip Multi Processor (CMP). NoC accounts for a significant portion of the total power consumed by a CMP. In a standard NoC system, only a fraction of power dissipation occurs due to static/leakage, while the rest is due to dynamic power. Dynamic dissipation includes self-switching and coupling switching dissipations, with the latter accounting for a significant part of total power dissipated. Several coding methods exist to minimize this dynamic power dissipation in NoC links. In this paper, we propose Algorithm 1 to reduce self-switching transitions and Algorithm 2 & 3 to lower coupling switching transitions in between the serial links, with Encoder/decoder modules placed at Network-Interface(NI) level. Simulations done on Xilinx Vivado design suite showed a maximum reduction of 64% in coupling switching activity compared to existing schemes.

A cost effective test structure to check a correctness of cache performance in chip multiprocessors (CMPs) is developed in this work. The basis of the work has been the cellular automata (CA) structure proposed by von Neumann in 1950's. The theory of 1-dimentional 3-neighborhood null boundary CA is developed to monitor the behavior of each of the processors cache in CMPs. The special class of single length cycle attractor cellular automata accepts the (March) read/write status of cache word/line and evaluates to decide on the inaccurate functioning of a cache module. In this way, the inability of the classical design to identify defective behavior of CMPs cache is overcome. The design further enables identification of the region of defective cache module in the CMPs.

Power dissipation becomes an important issue in modern microprocessors such as chip multiprocessors (CMPs). Especially as the process technology advances below 90nm, the leakage power consumption becomes dominant in the total power dissipation, thus reducing the leakage power consumption is an important design goal for low-power CMPs. In particular, since most CMPs employ a large L2 cache, reducing the leakage power consumption of the L2 cache is critical in realizing low-power CMPs.In this paper, we propose a leakage-aware on-chip L2 cache organization called LACS. The proposed LACS, like the existing RACS organization, is based on a private L2 cache organization with an inter-L2 cache sharing support. However, unlike the RACS organization, which determines a peer L2 cache block for an inter-L2 cache sharing based on the reusability of the evicted L2 block and performance implications of peer L2 cache blocks, the LACS organization considers both the performance and leakage. The LACS organization reduces the leakage power consumption significantly over the leakage-oblivious RACS organization while achieving a similar performance gain over a private L2 cache organization. Experimental results show that the proposed LACS technique reduces the energy consumption by 23.6% and improves the energy delay product by 18.6% on average over the existing RACS scheme.

3D NOC for many-core processors

Non-sinusoidal voltage in electrical networks is one of the most pressing problems in the field of power quality. In non-sinusoidal modes in electrical networks, in addition to losses of active power at the fundamental frequency, i.e. at the 1-st harmonic, active power losses occur at frequencies that are multiples of the fundamental frequency, corresponding to harmonics from 2 to 40. Additional harmonic active power losses increase losses in electrical networks, creating economic damage for both energy companies and consumers. The paper provides a review of the literature on the topic under consideration. A methodological approach is proposed to assess additional active power losses in overhead power lines. Based on the methodological approach, an analysis of the power quality indicators characterizing the non-sinusoidal mode, measured at the point of connection of 110 kV transmission line to the electrical network, was carried out, additional active power losses were determined.

The design inaccuracy (fault) in predictors can cause huge power loss in processor posing serious threat to the designers. The objective of the current analysis of fault impact on the processor power consumption is to devise a methodology for diagnosis of the faulty module in a branch predictor. It is effectively the first step for identification of DPL (design to avoid power loss) in a processor. Exhaustive analysis reveals that the undoubted diagnosis of design inaccuracies, that is effective for DPL, can be formalized in a TWO-LEVEL predictor by sensing the power drainage from processor.

Chip multiprocessors - also called multi-core microprocessors or CMPs for short - are now the only way to build high-performance microprocessors, for a variety of reasons. Large uniprocessors are no longer scaling in performance, because it is only possible to extract a limited amount of parallelism from a typical instruction stream using conventional superscalar instruction issue techniques. In addition, one cannot simply ratchet up the clock speed on today's processors, or the power dissipation will become prohibitive in all but water-cooled systems. Compounding these problems is the simple fact that with the immense numbers of transistors available on today's microprocessor chips, it is too costly to design and debug ever-larger processors every year or two. CMPs avoid these problems by filling up a processor die with multiple, relatively simpler processor cores instead of just one huge core. The exact size of a CMPs cores can vary from very simple pipelines to moderately complex superscalar processors, but once a core has been selected the CMPs performance can easily scale across silicon process generations simply by stamping down more copies of the hard-to-design, high-speed processor core in each successive chip generation. In addition, parallel code execution, obtained by spreading multiple threads of execution across the various cores, can achieve significantly higher performance than would be possible using only a single core. While parallel threads are already common in many useful workloads, there are still important workloads that are hard to divide into parallel threads. The low inter-processor communication latency between the cores in a CMP helps make a much wider range of applications viable candidates for parallel execution than was possible with conventional, multi-chip multiprocessors; nevertheless, limited parallelism in key applications is the main factor limiting acceptance of CMPs in some types of systems.

This uses Wattch and the SPEC 2000 integer and floating-point benchmarks to explore the role of branch predictor organization in power/energy/performance trade offs for processor design. Even though the direction predictor by itself represents less than 1 percent of the processor's total power dissipation, prediction accuracy is nevertheless a powerful lever on processor behavior and program execution time. A thorough study of branch predictor organizations shows that, as a general rule, to reduce overall energy consumption in the processor, it is worthwhile to spend more power in the branch predictor if this results in more accurate predictions that improve running time. This not only improves performance, but can also improve the energy-delay product by up to 20 percent. Three techniques, however, can reduce power dissipation without harming accuracy. Banking reduces the portion of the branch predictor that is active at any one time. A new on-chip structure, the prediction probe detector (PPD), uses predecode bits to entirely eliminate unnecessary predictor and branch target buffer (BTB) accesses. Despite the extra power that must be spent accessing it, the PPD reduces local predictor power and energy dissipation by about 31 percent and overall processor power and energy dissipation by 3 percent. These savings can be further improved by using profiling to annotate branches, identifying those that are highly biased and do not require static prediction. Finally, we explore the effectiveness of a previously proposed technique, pipeline gating, and find that, even with adaptive control based on recent predictor accuracy, pipeline gating yields little or no energy savings.

Today's general-purpose processors are increasingly using multithreading in order to better leverage the additional on-chip real estate available with each technology generation. Simultaneous multi-threading (SMT) was originally proposed as a large dynamic superscalar processor with monolithic hardware structures shared among all threads. Inters hyper-threaded Pentium 4 processor partitions the queue structures among two threads, demonstrating more balanced performance by reducing the hoarding of structures by a single thread. IBM's Power5 processor is a 2-way chip multiprocessor (CMP) of SMT processors, each supporting 2 threads, which significantly reduces design complexity and can improve power efficiency. This paper examines processor partitioning options for larger numbers of threads on a chip. While growing transistor budgets permit four and eight-thread processors to be designed, design complexity, power dissipation, and wire scaling limitations create significant barriers to their actual realization. We explore the design choices of sharing, or of partitioning and distributing, the front end (instruction cache, instruction fetch, and dispatch), the execution units and associated state, as well as the L1 Dcache banks, in a clustered multi-threaded (CMT) processor. We show that the best performance is obtained by restricting the sharing of the L1 Dcache banks and the execution engines among threads. On the other hand, significant sharing of the front-end resources is the best approach. When compared against large monolithic SMT processors, a CMT processor provides very competitive IPC performance on average, 90-96% of that of partitioned SMT while being more scalable and much more power efficient. In a CMP organization, the gap between SMT and CMT processors shrinks further, making a CMP of CMT processors a highly viable alternative for the future