Evaluating reliability through soft error triggered exceptions at ARM Cortex-A9 microprocessor

CAFI: A Configurable location-Aware Fault Injection technique for software reliability assessment against soft errors

PTM-based hybrid error-detection architecture for ARM microprocessors

Cross-layer reliability is becoming the preferred solution when reliability is a concern in the design of a microprocessor-based system. Nevertheless, deciding how to distribute the error management across the different layers of the system is a very complex task that requires the support of dedicated frameworks for cross-layer reliability analysis. This paper proposes SyRA, a system-level cross-layer early reliability analysis framework for radiation induced soft errors in memory arrays of microprocessor-based systems. The framework exploits a multi-level hybrid Bayesian model to describe the target system and takes advantage of Bayesian inference to estimate different reliability metrics. SyRA implements several mechanisms and features to deal with the complexity of realistic models and implements a complete tool-chain that scales efficiently with the complexity of the system. The simulation time is significantly lower than micro-architecture level or RTL fault-injection experiments with an accuracy high enough to take effective design decisions. To demonstrate the capability of SyRA, we analyzed the reliability of a set of microprocessor-based systems characterized by different microprocessor architectures (i.e., Intel x86, ARM Cortex-A15, ARM Cortex-A9) running both the Linux operating system or bare metal in the presence of single bit upsets caused by radiation induced soft errors. Each system under analysis executes different software workloads both from benchmark suites and from real applications.

Most aircrafts is driven by chemic energy which is released in the combustion process. For improving the capability of engine and controlling the running on-time, the processes of fuel physics and chemistry need to be analysis by kinds of high quality sensor. In the research of designing and improving the processes of fuel physics and chemistry, the concentration, temperature and velocity of kinds of gas in the combustor need to be detected and measured. In addition, these engines and research equipments are always in the harsh environment of high temperature, high pressure and high speed. The harsh environment needs the sensor to be high reliability, well repetition, no cross- sensitivity between gases, and the traditional measurement system can't satisfy the metrical requirement well. Tunable diode laser absorption spectroscopy (TDLAS) analytic measurement technology can well satisfy the measurement in the harsh environment, which can support the whole measurement plan and high quality measurement system. Because the TDLAS sensor has the excellence of small bulk, light weight, high reliability and well specifically measurement, the TDLAS measurement technology has wide prospects. Different from most measurements, only a beam of laser can be pass through the measured environment by TDLAS, and the measurement equipment needn't be set in the harsh environment. So, the TDLAS equipment can't be interrupted by the measured equipment. The ability of subsistence in the harsh environment is very valuable, especially in the measurement on the subject of aerospace with environment of high speed, combustion and plasma. This paper focuses on the collecting the articles on the subject of oxygen detection of TDLAS. By analyzing the research and results of the articles, we conclude the central issues, difficulties and results. And we can get some instructive conclusions.

A novel BRAM content accessing and processing method based on FPGA configuration bitstream

Test program generation and simulation is the most widely used approach to functional verification of microprocessors. High complexity of modern hardware designs creates a demand for automated tools that are able to generate test programs covering non-trivial situations in microprocessor functioning. The majority of such tools use test program templates that describe scenarios to be covered in an abstract way. This provides verification engineers with a flexible way to describe a wide range of test generation tasks with minimum effort. Test program templates are developed in special domain-specific languages. These languages must fulfill the following requirements: (1) be simple enough to be used by verification engineers with no sufficient programming skills; (2) be applicable to various microprocessor architectures and (3) be easy to extend with facilities for describing new types of test generation tasks. The present work discusses the test program template description language used in the reconfigurable and extensible test program generation framework MicroTESK being developed at ISP RAS. It is a flexible Ruby-based domain-specific language that allows describing a wide range of test generation tasks in terms of hardware abstractions. The tool and the language have been applied in industrial projects dedicated to verification of MIPS and ARM microprocessors.

Fault injection in early microarchitecture-level simulation CPU models and beam experiments on the final physical CPU chip are two established methodologies to access the soft error reliability of a microprocessor at different stages of its design flow. Beam experiments, on one hand, estimate the devices expected soft error rate in realistic physical conditions by exposing it to accelerated particles fluxes. Fault injection in microarchitectural models of the processor, on the other hand, provides deep insights on faults propagation through the entire system stack, including the operating system. Combining beam experiments and fault injection data can deliver deep insights about the devices expected reliability when deployed in the field. However, it is yet largely unclear if the fault injection error rates can be compared to those reported by beam experiments and how this comparison can lead to informed soft error protection decisions in early stages of the system design.

All-Programmable System-on-Chips (APSoCs) constitute a compelling option for employing applications in radiation environments thanks to their high-performance computing and power efficiency merits. Despite these advantages, APSoCs are sensitive to radiation like any other electronic device. Processors embedded in APSoCs, therefore, have to be adequately hardened against ionizing-radiation to make them a viable choice of design for harsh environments. This paper proposes a novel lockstep-based approach to harden the dual-core ARM Cortex-A9 processor in the Xilinx Zynq-7000 APSoC against radiation-induced soft errors by coupling it with a MicroBlaze TMR subsystem in the programmable logic (PL) layer of the Zynq. The proposed technique uses the concepts of checkpointing along with roll-back and roll-forward mechanisms at the software level, i.e. software redundancy, as well as processor replication and checker circuits at the hardware level (i.e. hardware redundancy). Results of fault injection experiments show that the proposed approach achieves high levels of protection against soft errors by mitigating around 98% of bit-flips injected into the register files of both ARM cores while keeping timing performance overhead as low as 25% if block and application sizes are adjusted appropriately. Furthermore, the incorporation of the roll-forward recovery operation in addition to the roll-back operation improves the Mean Workload between Failures (MWBF) of the system by up to ≈19% depending on the nature of the running application, since the application can proceed faster, in a scenario where a fault occurs, when treated with the roll-forward operation rather than roll-back operation. Thus, relatively more data can be processed before the next error occurs in the system.

Nanoscale field-programmable gate array (FPGA) circuits are more prone to radiation-induced effects in harsh environments because of their memory-based reconfigurable logic fabric. Consequently, for mission- or safety-critical applications, appropriate fault-tolerance techniques are widely employed. The most commonly applied technique for hardening FPGAs against radiation-induced upsets is triple modular redundancy (TMR). Voting circuits used in TMR implementations are decentralized and consensus is calculated from the redundant outputs off-chip. However, if there are an insufficient number of pins available on the chip carrier, the TMR system must be reduced to an on-chip unprotected simplex system, meaning voters used at those locations become single point of failure. In this paper, we propose a self-checking voting circuit for increased reliability consensus voting on FPGAs. Through fault injection and reliability analyses, we demonstrate that the proposed voter, which utilizes redundant voting copies, is approximately 26% more reliable than an unprotected simplex voter when reliability values of voters over normalized time are averaged.

Electronic computing systems are integrating modern multicore processors and GPUs aiming to perform complex software stacks in different life-critical systems, including health devices and emerging self-driving cars. Such systems are expected to experience at least one soft error per day in the near future, which may lead to life-threatening failures. To prevent these failures, critical system must be tested and verified while under realistic workloads. This paper presents four novel non-intrusive fault injection techniques that enable full fault injection control and inspection of multicore systems behavior in the presence of faults. Proposed techniques were integrated into a fault injection framework and verified through a real automotive case study with up to 43 billions instructions. Results show that compared to traditional methods, the new techniques can increase the efficiency of fault injection campaigns during early development phase by 32.28%.

This book introduces the concepts of soft errors in FPGAs and GPUs. The chapters cover radiation effects in FPGAs, fault-tolerant techniques for FPGAs, use of COTS FPGAs in aerospace applications, experimental data of FPGAs under radiation, FPGA embedded processors under radiation, and fault injection in FPGAs. Since dedicated parallel processing architectures such as GPUs have become more desirable in aerospace applications due to high computational power, GPU analysis under radiation is also discussed.

In order to improve the safety of the operation of the hydrogen-cooled generator and ensure the stable operation parameters of the hydrogen as the cooling medium, this paper presents a low-cost and high-performance hydrogen quality monitoring system for the hydrogen-cooled generator with ARM microprocessor as the core. The system consists of a data terminal system and a cloud monitoring platform system. The distributed terminal uses ARM as the main controller to monitor the main parameters of hydrogen, including hydrogen purity, temperature, humidity and so on. The field sensor converts the signal into ARM and then transfers it through the 4G wireless communication network to the online real-time monitoring platform system running in private cloud mode. The monitoring platform system can manage and analyze the data, and the system can communicate with the DCS system of the power plant, and obtain the hydrogen quality safety evaluation result through the safety evaluation model. The system realizes the remote monitoring and data analysis of the hydrogen-cooled generator, improves the quality of hydrogen quality control, and reduces the cost of generator maintenance and technological innovation. The system has high reliability and strong expansibility, which can meet the monitoring requirements of hydrogen gas generator hydrogen quality, which provides a guarantee for the safe and efficient operation of power plant.

What is the probability that the execution state of a given microprocessor running a given application is correct, in a certain working environment with a given soft-error rate? Trying to answer this question using fault injection can be very expensive and time consuming. This paper proposes the baseline for a new methodology, based on microprocessor error probability profiling, that aims at estimating fault injection results without the need of a typical fault injection setup. The proposed methodology is based on two main ideas: a one-time fault-injection analysis of the microprocessor architecture to characterize the probability of successful execution of each of its instructions in presence of a soft-error, and a static and very fast analysis of the control and data flow of the target software application to compute its probability of success. The presented work goes beyond the dependability evaluation problem; it also has the potential to become the backbone for new tools able to help engineers to choose the best hardware and software architecture to structurally maximize the probability of a correct execution of the target software.

Some types of electronic systems are working in the environment with an increased occurrence of faults such as space, aerospace or medical systems. Faults in these systems can lead to the failure of the whole system and, can cause high economical losses or endanger human health. Fault tolerance is one of the techniques, the goal of which is to avoid such situations. This paper presents an approach to fault-tolerant data-paths design that is based on the modification of High-level Synthesis (HLS) input specification. The description and evaluation of the impacts of some HLS optimization methods are demonstrated, in the paper as well. Higher reliability is achieved through the modification of input description in the C++ programming language which the HLS synthesis tools are based on. Our work targets SRAM-based FPGAs that are prone to Single Event Upsets (SEUs). For the evaluation of the proposed method we use our evaluation platform, which allows us to analyze fault tolerance properties of the Design Under Test (DUT). The evaluation platform is based on functional verification in combination with fault injection.

As a type of VLSI, the DSP chip has been widely used in avionics systems where its application can effectively improve the integration of avionics systems. In the testability test, this high level of integration leads to a reduction in the operability of fault injection. To counter this limitation, a DSP chip IO fault injection technique based on boundary scan is proposed. Firstly, the real-time data of the fault injection object is captured through a boundary scan chain. Next, the fault injection data sequence is generated in combination with the control instruction, and these data sequences are written into the boundary scan chain register. Finally, these data are updated to the IO pins of the fault injection object and these pins controlled to generate logic changes and complete the fault injection. The experimental results show that the method is simple to operate and is not affected by the package and structure of the DSP chip; it can effectively improve fault injection efficiency.