Evaluating the Impact of Process Variation on RRAMs

ABSTRACTThe rapid growth of scaling and integration of nano-scale digital circuits is hardly tracked by the analog circuits which require additional passive components for fabrication. Mixed-signal Complementary Metal Oxide Semiconductor (CMOS) technologies are released with some delays after digital CMOS technologies, due to the issues related to integration of analog components. This urges the designers to consider using the same digital CMOS technology for integration of advanced analog circuits like continuous-time filters. As such, this article presents an area-efficient Gm–C filter made from MOS devices only. Instead of classical metal–insulator–metal capacitors, the proposed filter exploits the available compact-size MOS devices as capacitor. This modification makes the filter design compatible to any low-cost digital CMOS process. Besides, the 3-dB cut-off frequency of the filter can now be changed by varying the size of MOS capacitors. The effectiveness of the new design approach is validated through simulation of a fifth-order elliptic low-pass filter with a cut-off frequency of 1 MHz in 90-nm CMOS technology. The new filter dissipates around 115 µW from a 1.0 V power supply, and the sensitivity of its cut-off frequency is kept as low as 6% over various process and temperature corners.

In today’s technology, optical networking plays a vital role in reducing data losses, thereby providing higher data rates between the transreceivers. The very large scale integration circuits in the modulator–demodulator (MODEM) usually fabricated using complementary metal oxide semiconductor (CMOS) technology have serious scaling limitations; hence, device scaling beyond 65 nm technology becomes highly challenging. Quantum-dot cellular automata (QCA) is one of the most promising nanotechnologies that enable areas of smaller size, i.e. 60% less design area than the CMOS technology, with capability to produce high speed by taking less cycles compared with the other CMOS designs to reduce scaling issues. The QCA-based designs are considered as the best alternative solutions to the transistor-based (CMOS) designs. This paper deals with the implementation of the logic gates NOT, AND, OR, NAND, NOR, XOR and XNOR using both CMOS and QCA technologies, while the QCA allows more possible design structures for each logic gate to enable optimization of the area. Finally, the proposed QCA-based logic gate design and CMOS-based designs are compared in terms of the design area, cell count and the speed of the designs. QCA designer 2.0.3 and virtuoso CADENCE Computer-Aided Design tools are used for carrying out the work.

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

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Decimal arithmetic is gaining more attention by researchers due to their importance in many human-centric applications. Hardware implementations of decimal arithmetic are preferable over their software counterparts as the former leads in performance especially when it comes to real-time applications. Decimal addition is a main decimal operation as most of the other decimal operation can be implemented using decimal addition. Complementary Metal Oxide Semiconductor (CMOS) technology has the advantage of reducing the average power consumption and the propagation delay in digital systems. Decimal adders can be designed as a ripple carry addition (RCA) structure or as a carry look-ahead addition (CLA) structure with the latter being faster with extra hardware cost. This work proposes two CMOS-based carry look-ahead decimal adders (CLDAs) that can be used within any decimal arithmetic unit. Operands of 1-digit size, 2-digit size, 3-digit size, and 4-digit size are investigated. The Boolean logic for each of the proposed CLDAs is developed and the CMOS realization is provided. The circuit of each of the proposed CLDAs is simulated with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$45~nm$ </tex-math></inline-formula> technology library using the LT-SPICE spice simulation tool. The simulation shows promising results in terms of speed, power, and power delay product (PDP).

In this article, a three-stage and five-stage voltage-controlled oscillator (VCO) using current starved configuration has been proposed. Among the two, only a three-stage VCO gives the required bandwidth of 5 GHz. Current starved VCO is designed using complementary metal oxide semiconductor (CMOS) technology. The oscillating output frequency bandwidth (2–7 GHz) is considered as the main objective for the proposed circuit. The proposed three-stage VCO circuit uses low supply voltage of 1 V, low power of 29.93 uW. Transient analysis and periodic steady state (PSS) analysis are performed, and after simulation, a wide frequency bandwidth of 5 GHz was obtained. The phase noise for the three-stage VCO at 1 GHz is −132 dBc/Hz. The circuit has been designed in Cadence Virtuso using gpdk 45 nm CMOS technology with supply voltage of 1 V.

We implanted high energy boron to create a heavily doped ground plane in Cz wafers in order to replace p/p/sup +/ episubstrates in deep submicron complementary metal-oxide semiconductor (CMOS) technology. Devices manufactured on Cz wafers with a 1.5 or 1.6 MeV, 1/spl times/10/sup 15/ cm/sup -2/ boron implanted ground plane have superior latch-up immunity as compared to devices on epiwafers. Improvements in latch-up suppression were observed for all isolation spacings. Diode leakage was lower in high dose buried-layer substrates than in episubstrates, while gate oxide integrity was equivalent. For the first time, buried layer substrates have been shown to duplicate or exceed the performance of episilicon simultaneously for all relevant CMOS transistor and circuit parameters.

A high-performance 0.25- mu m CMOS (complementary metal oxide semiconductor) technology with a reduced operating voltage of 2.5 V is presented. A loaded ring oscillator (NAND FI=FO=3. C/sub w/=0.2 pF) delay per stage of 280 ps achieved (W/sub eff//L/sub eff/=15 mu m/0.25 mu m), which is a 1.7 X improvement over 0.5- mu m CMOS technology. At shorter channel lengths (0.18 mu m), a CMOS stage delay of 38 ps for unloaded inverter ring oscillators and 185 ps for loaded NAND are demonstrated. A reduced operating voltage in the range of 2.2-2.5 V is chosen to optimize performance without compromising reliability. Shallow junctions with abrupt profiles are used to minimize device series resistance as well as gate-to-source/drain (S/D) overlap capacitance. Dural poly (n/sup +/ and p/sup +/) gates are used to avoid buried-channel operation pFETs, resulting in superior short-channel characteristics. Poly and S/D sheet resistances are lowered, using a thin salicide (TiSi/sub 2/) process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

The technological essence of silicon photonic integrated circuits is to utilize the mature complementary metal oxide semiconductor (CMOS) technology, or the processes compatible with CMOS technology, to monolithically integrate various kinds of photonic devices in silicon-on-insulator (SOI) substrate. The technology of silicon photonic integrated circuits can fabricate large-scale integrated photonic devices for mass production, providing innovative solutions to the ever-growing demands of high bandwidth, low manufacturing cost, low power consumption in data center, high performance computing center, artificial intelligence and cloud storage. Highspeed optical transceiver modules based on silicon photonic integrated circuits have been commercialized in recent years. Moreover, co-packaged optics (CPO) has become a hot topic and trend for the assembly solution of next generation high-speed switch, and is expected to replace the hot-pluggable optical transceiver modules in the near future.

As quantum processors grow in complexity, the focus is shifting towards the scaling of the entire quantum computing system, including the quantum hardware but as well the classical support electronics. Silicon-based quantum computing offers the enticing possibility that the quantum processor, the quantum-classical interface, and the classical layer can all, in principle, be manufactured using complementary metal-oxide semiconductor (CMOS) technology, creating an opportunity to move from distributed quantum-classical systems to integrated quantum computing solutions. Here, we review the state-of-the-art in spin-based quantum computing in silicon and present different approaches to help scale the technology using CMOS technology. We discuss the use of industry-manufactured silicon devices as the basic qubit element and present radio-frequency reflectometry techniques for fast high-fidelity spin readout. Finally, we show how quantum-classical co-integration can enable large-scale control and readout via frequency- and time-domain multiplexing.

Resistance random access memory (RRAM) based on resistive switching in metal oxides has attracted considerable attention as a promising candidate for next-generation nonvolatile memory due to its high operating speed, superior scalability, and low power consumption. However, some operating parameters of RRAM cannot meet the practical requirement, which impedes its commercialization. A lot of experimental results show that doping is an effective method of improving the performance of RRAM, while the study on the physical mechanism of doping is rare. It is generally believed that the formation and rupture of conducting filaments, caused by the migration of oxygen vacancies under electric field play a major role in resistive switching of metal oxide materials. In this work, the first principle calculation based on density functional theory is performed to study the effects of transition metal element X (X=Mn, Fe, Co, and Ni) doping on the migration barriers and formation energy of oxygen vacancy in ZnO. The calculation results show that the migration barriers of both the monovalent and divalent oxygen vacancy are reduced significantly by Ni doping. This result indicates that the movement of oxygen vacancies in Ni doped ZnO is easier than in undoped ZnO RRAM device, thus Ni doping is beneficial to the formation and rupture of oxygen vacancy conducting filaments. Furthermore, the calculation results show that the formation energy of the oxygen vacancy in ZnO system can be reduced by X doping, especially by Ni doping. The formation energy of the oxygen vacancy decreases from 0.854 for undoped ZnO to 0.307 eV for Ni doped ZnO. Based on the above calculated results, Ni doped and undoped ZnO RRAM device are prepared by using pulsed laser deposition method under an oxygen pressure of 2 Pa. The Ni doped ZnO RRAM device shows the optimized forming process, low operating voltage (0.24 V and 0.34 V for Set and Reset voltage), and long retention time (&gt;104 s). Set and Reset voltage in Ni doped ZnO device decrease by 80% and 38% respectively compared with those in undoped ZnO device. It is known that the density of oxygen vacancies in the device is dependent on the oxygen pressure during preparation. The Ni doped ZnO RRAM device under a higher oxygen pressure (5 Pa) is also prepared. The Ni doped ZnO RRAM device prepared under 5 Pa oxygen pressure shows a little higher Set and Reset voltage than the device prepared under 2 Pa oxygen pressure, while the operating voltages are still lower than those of undoped ZnO RRAM. Thus, the doping effect in the ZnO system is affected by the density of oxygen vacancies in the device. Our work provides a guidance for optimizing the performance of the metal oxide based RRAM device through element doping.

Although sorting networks have extensively been reported in literature (Batcher, 1962), there are a few references that cover a detailed explanation about their VLSI (Very Large Scale of Integration) realization in CMOS (Complementary Metal-Oxide-Semiconductor) technology (Turan et al., 2003). From an algorithmic point of view, a sorting network is defined as a sequence of compare and interchange operations depending only on the number of elements to be sorted. From a hardware perspective, sorting networks can be visualized as combinatorial circuits where a set of denoted compare-swap (CS) circuits can be connected in accordance to a specific network topology (Knuth, 1997). In this chapter, the design of sorting networks in CMOS technology with applicability to VLSI design is approached at block, transistor, and layout levels. Special attention has been placed to show the hierarchical structure observed in sorting schemes where the so called CS circuit constitutes the fundamental standard cell. The CS circuit is characterized through SPICE simulation making a particular emphasis in the silicon area and delay time parameters. In order to illustrate the inclusion of sorting networks into specific applications, like signal processing and nonlinear function evaluation, two already reported examples of integrated circuit designs are provided (Agustin et al., 2011; Jimenez et al., 2011).

This work presents the advanced version of novel POSFET (Piezoelectric Oxide Semiconductor Field Effect Transistor) devices based tactile sensing chip. The tactile sensing chip in the new version, presented here, has been fabricated using CMOS (Complementary Metal Oxide Semiconductor) technology. The chip consists of 4 × 4 POSFET touch sensing devices, four temperature diodes, and the electronic circuitry comprising of multiplexers, current mirrors, high compliance current sinks and voltage output buffers. The on chip POSFET devices have linear response in the tested dynamic contact forces range of 0.01-3N and the sensitivity (without amplification) is 102.4 mV/N.

In this paper. The effect of intradie process variations oy the delay of tapered buffers designed in static CMOS logic style is analyzed in depth. An analytical delay model accounting for the dependency of variations on transistor sizing, load and input capacitance requirement is derived for the single stage. Then, this model is extended to the case of N-stage tapered buffers. The closed-form delay expressions includin. The contribution of intradie variations permit to gain an insight int. The impact of process variations oy the performance of tapered buffers. Monte Carlo simulations on a 90-nm technology including layout parasitica are performed to validat. The analysis. Results are shown to agree well wit. The expressions derived, thereby confirmin. The validity oy the underlying assumptions, as well at the suitability oy the proposed models for design purposes. © 2009 IEEE.