Evaluation of Cache Coherence Mechanisms for Multicore Processors

Due to modern technology trends such as decreasing feature sizes and lower voltage levels, fault tolerance is becoming increasingly important in computing systems. Shared memory in modern multiprocessor systems is supported by cache coherence mechanisms. The correctness of cache coherence of the system is crucial for the data integrity. This work proposes an error detection scheme for snooping-based cache coherence protocols. For the widely used MESI coherence protocol, the proposed method does not introduce any performance overhead. Only a limited amount of additional hardware is required. Existing systems can be easily extended to support the proposed technique. Almost all single faults that are able to affect data integrity in the system are covered, with the exception of a few very rare cases. Experimental results involving fault injection do not encounter any undetected faults leading to corrupted application output.

Computer systems are extensively being used in today’s era and the advancement in computer systems has led to the evolution of various technologies. As the efficiency of the computer systems is to be enhanced, the usage of cache memory becomes a must. The cache memory problems occur when multiprocessor systems are used. When multiple processors are processors share a common memory pool, the problem of cache coherence occurs. Cache coherence is a state in which the cache memories of the processors must stay in coherence with each other. The data should be updated in all the cache systems. Various protocols are used to ensure cache coherence. This study delineates the cache memory architecture, cache coherence, and the issues that arise due to non-consistent data in the cache of multiprocessor systems. Moreover, this study also delineates the protocols of the cache coherence and also describes in detail the MISE protocol. This study will provide an in-depth review of cache, cache coherence, and the issues associated with cache coherence along with the solution.

Multipliers have been key and critical components for most application-specific and general-purpose computer architectures. However, these architectures have been transitioning towards multiple cores that can process large amounts of data through parallel approaches to computation. Unfortunately, traditional arithmetic functional units that worked well for single-core architectures have the side-effect of incurring large amounts of area and power. Consequently, multi-core computer architecture need new ways of thinking about increased throughput to handle large amounts of data. This paper presents a recursive high radix divide unit that is modified to handle both multiplication and division targeted at multi-core architectures. Results are obtained with a 65nm technology and show a significant decrease in area and power while still maintaining a low total latency by utilizing high radix encoding within the functional unit. More importantly, because the datapath unit requires complex recoding, it does not increase its latency as the bit size increases. Therefore, these units can occupy low amounts of area while still maintaining high amounts of processing power.

To satisfy the increasing demands in computing throughput, new processor designs are frequently expanding their support for parallel operations, including multiple memory controllers, caches, and various I/O devices, but especially multiple processor cores. For developers of real-time embedded systems with security and/or safety-critical computing requirements, the advent of processors that include multiple cores has created a fundamental problem: how to satisfy certification considerations so that safety and/or security related applications can execute on real-time multi-core based partitioning enforcing systems. This paper examines some architectural considerations that may be taken into account as part of safety and/or security certification of a partitioning operating system that supports the scheduling of multiple applications on a multi-core processor. In particular, it covers a set of considerations and challenges associated with using multiple cores as part of an architecture that supports simultaneous execution of applications on different cores and as part of an architecture that supports simultaneous use of multiple cores cooperatively within an application. This includes high-level considerations of safety and security topics such as, shared resource management, caching, covert channels, and fault management. In addition, it examines the use of synchronous time-scheduling controls as a means to resolve some of the safety and security related issues. This paper, by examining and detailing some of the high-level safety and security considerations associated with multi-core processor architectures, is intended to demonstrate the benefits of utilizing synchronous time-scheduling controls across the entire multi-core processor as a means to resolve some of the issues. Developers of real-time embedded systems can maximize the benefit of multi-core processors through understanding the types of architectural features that may be necessary to resolve specific safety and/or security issues.

Processing-in-memory (PIM) architectures cannot use traditional approaches to cache coherence due to the high off-chip traffic consumed by coherence messages. We propose LazyPIM , a new hardware cache coherence mechanism designed specifically for PIM. LazyPIM uses a combination of speculative cache coherence and compressed coherence signatures to greatly reduce the overhead of keeping PIM coherent with the processor. We find that LazyPIM improves average performance across a range of PIM applications by 49.1 percent over the best prior approach, coming within 5.5 percent of an ideal PIM mechanism.

Aiming at the Cache coherence problem that brings by multiple processor cores of CMP(Chip multiprocessors) sharing the single memory space, this paper introduces a new kind of Cache coherence--CSC(Coherence with SC-Cache) based on write-through and write-back mechanism, which contains SC-Cache (Shared Coherence Cache) module. Experiments show that the protocol reduces the number of bus transactions, to a certain extent improves the efficiency of processor data access.

Edge computing pushes the computational loads from the cloud to embedded devices, where data would be processed near the data source. Heterogeneous multicore architecture is believed to be a promising solution to fulfill the edge computational requirement. In FPGAs, the heterogeneous multicore is realized as multiple soft processor cores with custom processing elements. Since FPGA is a resource-constrained device, sharing the hardware resources among the soft processor cores can be advantageous. Some research has focused on the sharing resources among soft processors, but they do not study how much FPGA logic is minimized for a five-stage pipeline processor. This paper proposes the microarchitecture of a five-stage pipeline scalar processor that enables the sharing of functional units for execution among the multiple cores. We then investigate the performance and hardware resource utilization for a four-core processor. We find that sharing different functional units can save the LUT usage to 23.5% and DSP usage to 75%. We analyze the performance impact of sharing from the Embench benchmark program by simulating the same program in all four cores. Our simulation results indicate that based on the sharing configuration, the average performance drops from 2.9% to 22.3%.

Multi-core computer architectures are on the forefront in consumer electronics and adaptation in safety-critical applications such as avionics could be beneficial due to their potential increased performance. Yet, there are challenges to deploy cutting edge multi-core architectures for safety-critical applications. New computing architectures are more integrated and optimized for average cases. On the other side, safety-critical applications need to be designed for the worst case. For example, the impact of integrating critical applications is not fully understood yet, especially with respect to execution times of critical paths. This paper proposes and argues an approach to quantify the impact of integration of multiple independent applications onto multi-core platforms and evaluates the approach on a specific potential future avionics computing platform. Evaluation results focusing on execution estimates show that multi-core computers may be used for safety-critical applications, but the worst-case execution time (WCET) can be multiple times slower than the same application running on a single core without other cores running interfering applications. The actual factor is very dependent on the application's use of shared resources like memory.

In multicore and multicached architectures, cache coherence is ensured with a coherence protocol. However, the performance benefits of caching diminishes due to the cost associated with the protocol implementation. In this paper, we propose a novel technique to improve the performance of multithreaded programs running on shared-memory multicore processors by embracing approximate computing. Our idea is to relax the coherence requirement selectively in order to reduce the cost associated with a cache-coherence protocol, and at the same time, ensure a bounded QoS degradation with probabilistic reliability. In particular, we detect instructions in a multithreaded program that write to shared data, we call them Shared-Write-Access-Points (SWAPs), and propose an automated statistical analysis to identify those which can tolerate coherence faults. We call such SWAPs approximable. Our experiments on 9 applications from the SPLASH 3.0 benchmarks suite reveal that an average of 57% of the tested SWAPs are approximable. To leverage this observation, we propose an adapted cache-coherence protocol that relaxes the coherence requirement on stores from approximable SWAPs. Additionally, our protocol uses stale values for load misses due to coherence, the stale value being the version at the time of invalidation. We observe an average of 15% reduction in CPU cycles and 11% reduction in energy footprint from architectural simulation of the 9 applications using our approximate execution scheme.

Ideally, we could solve all memory performance problems by storing everything in high performance caches. However, the associated high-cost forces us to keep only a limited amount of working sets of data in these caches and the replacement of disposable blocks of data with the desired one is a fundamental property to caches. Ultimately, the performance of a cache is heavily influenced by the replacement policy it uses. In this paper, we conduct a comparative analysis of a few replacement policies currently in use from traditional strategies to the ones that attempt to emulate optimal replacement and simulate a few replacement strategies to test the performance of multilevel cache by configuring the cache memory subsystem in the Multi2sim simulator. We have focused on the shared nature of the last Level Cache (LLC) which includes many coherence problems. This is where directories and coherence protocols come into play. However, the blocks suffer when the directory entries are themselves evicted from the directory. In this paper, we look into a cache coherence mechanism that instead of evicting the block from the private caches when the directory entry is evicted, rather than storing the entry in the LLC slice. This guarantees freedom from the Directory Eviction Victim Blocks (DEVB). We analyze the performance of our proposed replacement technique, namely, coalesce private or spill shared (CPOSS) by varying the size and associativity of the sparse directory by providing the workload from Parsec, Splash2 and FFTW benchmarks and we observe that the CPOSS outperforms the existing least recently used (LRU) in slice LLC banks in Multicore processors.

Recently, a new paradigm has emerged for structuring distributed network applications: mobile agents programming. Mobile agents are mainly intended to be used for applications distributed over large scale (slow) networks because they allow saving communication costs by moving computation to the host on which the target data resides. In this paper, our work includes three parts: (1) we introduce mobile agent into large scale distributed file system: The mobile agent-based distributed file system (MADFS). MADFS uses mobile agents as the underlying facility for transfer, communication and synchronization; (2) we present a novel high-performance runtime codes leading mechanism for mobile agents in wide area network (WAN); (3) we present a novel cache coherency mechanism which is designed for MADFS: hierarchical and convergent cache coherency mechanism (HCCM). HCCM use mobile agent to effectively reduce the cache management overhead in distributed file system.

This paper proposes a novel parallel execution model for Bidirectional Recurrent Neural Networks (BRNNs), B-Par (Bidirectional-Parallelization), which exploits data and control dependencies for forward and reverse input computations. B-Par divides BRNN workloads across different parallel tasks by defining input and output dependencies for each RNN cell in both forward and reverse orders. B-Par does not require per-layer barriers to synchronize the parallel execution of BRNNs. We evaluate B-Par considering the TIDIGITS speech database and the Wikipedia data-set. Our experiments indicate that B-Par outperforms the state-of-the-art deep learning frameworks TensorFlow-Keras and Pytorch by achieving up to 2.34× and 9.16× speed-ups, respectively, on modern multi-core CPU architectures while preserving accuracy. Moreover, we analyze in detail aspects like task granularity, locality, or parallel efficiency to illustrate the benefits of B-Par.

This paper presents a new solution to the group mutual exclusion problem recently posed by Joung. In this problem, processes repeatedly request access to various "sessions." It is required that distinct processes are not in different sessions concurrently, that multiple processes may be in the same session concurrently, and that each process that tries to enter a session is eventually able to do so. This problem is a generalization of the mutual exclusion and readers-writers problems. Our algorithm and its correctness proof are substantially simpler than Joung's. This simplicity is achieved by building upon known solutions to the more specific mutual exclusion problem. Our algorithm also has various advantages over Joung's, depending on the choice of mutual exclusion algorithm used. These advantages include admitting a process to its session in constant time in the absence of contention, spinning locally in Cache Coherent (CC) and Nonuniform Memory Access (NUMA) systems, and improvements in the complexity measures proposed by Joung.

The rapid advances in multi-core architecture and the predicted emergence of 100-core personal computers bring new appeal to volunteer computing. The availability of massive compute power under-utilized by personal computing tasks is a blessing to volunteer computing customers. Meanwhile the reduced performance impact of running a foreign workload, thanks to the increased hardware parallelism, makes volunteering resources more acceptable to PC owners. In addition, we suspect that with aggressive volunteer computing, which assigns foreign tasks to active computers (as opposed to idle ones in the common practice), we can obtain significant energy savings. In this paper, we assess the efficacy of such aggressive volunteer computing model by evaluating the energy saving and performance impact of co-executing resource-intensive foreign workloads with native personal computing tasks. Our results from executing 30 native-foreign workload combinations suggest that aggressive volunteer computing can achieve an average energy saving of around 52% compared to running the foreign workloads on high-end cluster nodes, and around 33% compared to using the traditional, more conservative volunteer computing model. We have also observed highly varied performance interference behavior between the workloads, and evaluated the effectiveness of foreign workload intensity throttling.

Lossless image compression plays a vital role in improving data storage and transmission efficiency without compromising data integrity. However, the throughput of current lossless compression and decompression systems remains limited and is unable to meet the growing demands of high-speed data transfer. To address this challenge, a previously proposed hybrid lossless compression and decompression algorithm has been implemented on an FPGA platform. This implementation significantly improves processing speed and efficiency. A multi-core system architecture is introduced, utilizing the processing system (PS) and programmable logic (PL) of a Xilinx Zynq-706 evaluation board. The PS handles coordination. The PL performs compression and decompression using multiple cores. Each core can process up to eight image tiles at the same time. The compression process is designed with a four-stage pipeline, and decompression is managed by a dynamic state machine to ensure optimized control. The parallel architecture and innovative algorithm design enable high-throughput operation, achieving compression and decompression rates of 480 Msubpixels/s and 372 Msubpixels/s, respectively. Through this work, a practical and high-performance solution for real-time lossless image compression is demonstrated.