Evaluation of Multi-threaded Processor Designs for Energy Efficient Embedded Systems

Abstract

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Multi-threaded processor designs enable high performance of a single processor core by exploiting both the thread-level and instruction-level parallelism. The performance gain is, however, at the cost of increasing energy consumption, which is not desirable to embedded systems. This paper investigates the energy efficiency of varied multi-threaded processor designs (with the coarse-grained and fine-grained thread switching schemes and different thread numbers). Our experiments, based on a six-stage PISA processor, show that in terms of potential energy saving the coarse-grained design is better than the fine-grained design. Furthermore, for the coarse-grained design, the thread number for the optimal energy efficiency is closely related to the memory access delay. When the memory access latency is small, the low-thread processor appears more energy efficient, When the memory delay increases the high-thread processor becomes superior.