Exchanged Crossed Cube: A Novel Interconnection Network for Parallel Computation

In large-scale supercomputers, the interconnection network plays a key role in system performance. Network topology highly defines the performance and cost of the interconnection network. Direct topologies are sometimes used due to its reduced hardware cost, but the number of network dimensions is limited by the physical 3D space, which leads to an increase of the communication latency and a reduction of network throughput for large machines. Indirect topologies can provide better performance for large machines, but at higher hardware cost. In this paper, we propose a new family of hybrid topologies, the k-ary n-direct s-indirect, that combines the best features from both direct and indirect topologies to efficiently connect an extremely high number of processing nodes. The proposed network is an n-dimensional topology where the k nodes of each dimension are connected through a small indirect topology of s stages. This combination results in a family of topologies that provides high performance, with latency and throughput figures of merit close to indirect topologies, but at a lower hardware cost. In particular, it doubles the throughput obtained per cost unit compared with indirect topologies in most of the cases. Moreover, their fault-tolerance degree is similar to the one achieved by direct topologies built with switches with the same number of ports.

Multistage interconnection networks are used as a medium for interconnecting processors and memories in multiprocessor systems. Multistage interconnection networks are an effective substitute for crossbar switches, used in telephone network systems and parallel computers, due to their low cost, better performance and easy maintainability. In this paper, we propose new fault-tolerant hybrid multistage interconnection networks obtained from shuffle exchange gamma interconnection network (SEGIN) and logical neighborhood network named as shuffle exchange gamma logical neighborhood interconnection network (SEGLNIN). We evaluated the performance of SEGLNIN in terms of disjoint paths, reliability and hardware cost and compared it with some well-known MINs like shuffle exchange network (SEN), shuffle exchange network with one extra stage (SEN +) and shuffle exchange network with two extra stages (SEN + 2), SEGIN-1, and SEGIN-2. The results illustrate that the performance of the proposed SEGLNIN is better than that of the compared networks in terms of reliability and disjoint paths.

Massively parallel computers have been used for high performance computation in advanced science and technology. The Hypercube (HC) network: has attractive properties such as strong connectivity, recursive interconnection, simple routing, and a good link complexity. However, as the number of processing elements (PEs) increases, the diameter and average distance of HC become large in proportion to a logarithm of the number of PEs. This causes a large latency in communication between PEs and consequently, it reduces system performance. To solve this problem, two approaches have been investigated. The first approach is a theoretical approach to find a network topology reducing a diameter and an average distance between PEs. The second approach reduces the physical distances between PEs by integrating a large interconnection on a small chip for a silicon wafer. In this paper, we propose a new interconnection network; The HCQ (Horizontal Rotate Crossed Cube) by taking into account a WSI implementation, Theoretical network properties such as the diameter, the average distance, a routing algorithm are discussed in detail. It is shown that HCQ is a suitable network topology for massively parallel computers for WSI.

Neurons in the brain form thousands of connections, or synapses, with one another, allowing signals to pass from one cell to the next. To activate a neuron, a high enough activating signal or ‘action potential’ must be reached. However, the accepted view of signal transmission assumes that the great majority of synapses are too weak to activate neurons. This means that often simultaneous inputs from many neurons are required to trigger a single neuron’s activation. However, such coordination is likely unreliable as neurons can react differently to the same stimulus depending on the circumstances. An alternative way of transmitting signals has been reported in turtle brains, where impulses from a single neuron can trigger activity across a network of connections. Furthermore, these responses are reliably repeatable, activating the same neurons in the same order. Riquelme et al. set out to understand the mechanism that underlies this type of neuron activation using a mathematical model based on data from the turtle brain. These data showed that the neural network in the turtle’s brain had many weak synapses but also a few, rare, strong synapses. Simulating this neural network showed that those rare, strong synapses promote the signal’s reliability by providing a consistent route for the signal to travel through the network. The numerous weak synapses, on the other hand, have a regulatory role in providing flexibility to how the activation spreads. This combination of strong and weak connections produces a system that can reliably promote or stop the signal flow depending on the context. Riquelme et al.’s work describes a potential mechanism for how signals might travel reliably through neural networks in the brain, based on data from turtles. Experimental work will need to address whether strong connections play a similar role in other animal species, including humans. In the future, these results may be used as the basis to design new systems for artificial intelligence, building on the success of neural networks.

Switching networks are widely used as core components in network switches and routers, and communication subsyetems in parallel computing systems. Most switching networks are multistage interconnection networks built with small-size switching elements. Nonblocking switching networks have been favored because of their capability of setting up any one-to-one I/O connections. There are three types of nonblocking networks: strictly nonblocking (SNB), wide-sense nonblocking(WSNB) and rearrangeable nonblocking (RNB). In both SNB and WSNB networks, a connection can be established from any idle input to any idle output without disturbing existing connections. In SNB networks any of available conflict-free paths for a connection can be chosen and inWSNB networks, however, a rulemust be followed to choose one. The high degree of connection capability in SNB and WSNB networks is at a high hardware cost. RNB networks, usually constructed with lower hardware cost, can establish a conflict-free path for the connection from any idle input to any idle output if the rearrangement of existing connections is allowed. Large-scale SNB and WSNB switching networks, which are suitable for circuit switching, are usually infeasible in practice due to their high cost. In contrast, rearrangeable networks are more scalable because of their much lower cost. However, rearrangeable networks are not suitable for circuit switching. Over the years, a rich theory of nonblocking switching networks has been developed. Unfortunately, no explicitly constructable optimal-cost SNB and WSNB network has been discovered. Known powerful nonblocking networks are either costly and unscalable, or very inefficient in routing connections. In this talk, we introduce the the notion of virtual nonblockingness and almost nonblockingness, and the concepts of virtual nonblocking (VNB) networks and almost nonblocking (ANB) networks.

Supercomputers are today made up of hundreds of thousands of nodes. The interconnection network is responsible for connecting all these nodes to each other. Different interconnection networks have been proposed; high performance topologies have been introduced as a replacement for the conventional topologies of recent decades. A high order, a low degree and a small diameter are the usual properties aimed for by such topologies. However, this is not sufficient to lead to actual hardware implementations. Network scalability and topology simplicity are two critical parameters, and they are two of the reasons why modern supercomputers are often based on torus interconnection networks (e.g., Fujitsu K, IBM Sequoia). In this paper we first describe a new topology, torus-connected cycles (TCCs), realizing a combination of a torus and a ring, thus retaining interesting properties of torus networks in addition to those of hierarchical interconnection networks (HINs). Then, we formally establish the diameter of a TCC, and deduce a point-to-point routing algorithm. Next, we propose routing algorithms solving the Hamiltonian cycle problem, and, in a two dimensional TCC, the Hamiltonian path one. Correctness and complexities are formally proved. The proposed algorithms are time-optimal.

Highly parallel systems are receiving significant attention to solve the large and complex problems. This has resulted in the emergence of many attractive interconnection network topologies. This paper introduces a new processor interconnection topology called STH (Scalable Twisted Hypercube) to counter the poor scalability of twisted hypercube. Its suitability for use as multiprocessor interconnection networks has also been explored. The various properties of the proposed topology have been analyzed and it has been compared with some other highly scalable topologies of interest on a number of interconnection networks evaluation parameters. With reduced diameter, better average distance, low traffic density, low cost, maximum number of links, high bisection width and tremendous scalability, STH is more suitable for Massively Parallel Systems. Procedures for routing and broadcasting on the proposed topology have also been discussed and a simple routing algorithm has been presented. The proposed interconnection network provides a great architectural support for parallel computing due to the concurrent existence of multiple LST(m) and TQn.

The increasing of the signaling technology motivated the research community to find alternative solutions to replace the sequential computing systems. These systems reached their limits, and it became an infeasible choice to manage the computational grand challenges. Thereby, many types of research have been conducted to improve a system with special characteristics able to cope with the new technology. Massively parallel computer (MPC) systems have been emerged to solve the complex computing challenges in parallel and concurrently. The performance of these systems is affected by the structure of the underlying interconnection network. Therefore, many designs of interconnection networks topologies have been presented looking for an optimal one. In this paper, we present the architecture of MMN which is a hierarchical interconnection network. The static and dynamic performance parameters of MMN have been evaluated in previous studies, and it provided good results compared to the conventional interconnection network topologies. This paper will focus on evaluating and determining the static cost-effective parameter of MMN which is the product of the relation between the node degree, network diameter, wiring complexity, and the total number of nodes in each network.

The Block Shift Network (BSN) is a new topology for interconnection networks in multiprocessor systems. BSN is a class of networks defined by several parameters, and has a constant number of links/node for some given parameters. Many popular networks such as the hypercube, the shuffle-exchange, and the complete networks, are instances of the BSN for different parameters. Performance of BSN has been evaluated through analysis, simulation, and design of typical parallel algorithms on it. The results indicate that BSN surpasses the hypercube in several respects while retaining most of the hypercube advantages, especially when the traffic has the locality property. As the size and complexity of a system increase, however, the reliability aspects become equally important and should be included in the system-performance study. This paper discusses the reliability issue of BSN. Several reliability measures, including network connectivity, network diagnosability, and 2-terminal reliability, are obtained through analysis. This paper shows that the BSN not only surpasses the hypercube in performance as confirmed before, but also has comparable reliability to the hypercube under similar conditions. BSN is also very flexible in balancing its cost and performance. One can increase two parameters to enhance the performance and reliability of the BSN, while it is impossible to do so in the hypercube once its size is fixed. The BSN can be an effective interconnection network for future parallel computer systems.

IntroductionResponse inhibition is one of the executive functions impaired in attention-deficit/hyperactivity disorder (ADHD). Increasing evidence indicates that altered functional and structural neural connectivity are part of the neurobiological basis of ADHD. Here, we investigated if adolescents with ADHD show altered functional connectivity during response inhibition compared to their unaffected siblings and healthy controls.MethodsResponse inhibition was assessed using the stop signal paradigm. Functional connectivity was assessed using psycho-physiological interaction analyses applied to BOLD time courses from seed regions within inferior- and superior frontal nodes of the response inhibition network. Resulting networks were compared between adolescents with ADHD (N = 185), their unaffected siblings (N = 111), and controls (N = 125).ResultsControl subjects showed stronger functional connectivity than the other two groups within the response inhibition network, while subjects with ADHD showed relatively stronger connectivity between default mode network (DMN) nodes. Stronger connectivity within the response inhibition network was correlated with lower ADHD severity, while stronger connectivity with the DMN was correlated with increased ADHD severity. Siblings showed connectivity patterns similar to controls during successful inhibition and to ADHD subjects during failed inhibition. Additionally, siblings showed decreased connectivity with the primary motor areas as compared to both participants with ADHD and controls.DiscussionSubjects with ADHD fail to integrate activation within the response inhibition network and to inhibit connectivity with task-irrelevant regions. Unaffected siblings show similar alterations only during failed stop trials, as well as unique suppression of motor areas, suggesting compensatory strategies. These findings support the role of altered functional connectivity in understanding the neurobiology and familial transmission of ADHD.

In an often-cited paper, A. Karp [1] commented on the “sorry state” of parallel programming, lamenting the difficulties in programming and debugging parallel programs on existing programming models. Indeed, a variety of programming models have been proposed with not entirely satisfactory results. In this note, we focus on the world of massively parallel shared memory machines and examine programming models for these machines. A shared memory parallel computer is one in which the processors communicate by reading and writing data words to a shared memory. We consider shared memory parallel computers with the following characteristics. Each processor has some fast, relatively small, private memory (e.g. registers, cache). There is a large shared memory composed of a series of memory banks that are accessible by all processors via an interconnection network. Each processor has one such memory bank which is local to it, i.e. it can access the bank without going through the interconnection network. The access time to a memory bank for a processor depends in part on the lengths of the links traversed and the number of hops in the path from the processor to the bank. Special coprocessors take care of interprocessor communication: both programmers and processors are relieved of the burden of routing the parallel requests to shared memory, including handling intermediate hops of requests traveling to their destinations. In order to overcome the high latency of accessing global memory, the parallel computer supports the pipelining of global memory accesses through the network. This implies that the interconnection network has sufficient bandwidth to handle the multiple requests per processor.

The optimization of multicast communication for regular interconnection networks (IN) has been the subject of many studies in the literature. Extensions, however, the analysis of IN with arbitrary topology and background traffic poses a great challenge. In this context, a novel heuristic algorithm for multicast communication is proposed for arbitrary IN with finite capacity and bursty background traffic. The scheme facilitates interprocess communication amongst parallel computers and Grid computing networks as well as local and wide area networks and it is applicable to a single-port mode of message passing communication. The scheme utilizes a queue-by-queue decomposition algorithm for arbitrary open queueing network models, based on the principle of maximum entropy, in conjunction with an information theoretic decomposition criterion and graph theoretic concepts. Evidence based on empirical studies indicates the suitability of the scheme for achieving an optimal multicast communication cost.

Our research targets the lack of ICT infrastructure in rural areas of Bangladesh. The research has the project to build a solar powered, low cost, fully fledged computer server from off-the-shelf components which will act as a network infrastructure for data collection, sharing and network distribution in rural areas of Bangladesh, even where electricity consistency is an issue. It is designed to create a Wi-Fi (2.4GHz) based network around the deployed area effectively creating a High Speed Local Area Network and provide ICT based services such as File Sharing, Instant Messaging, E-Education, Form Submission and a platform for any other on demand web & database services that are required by the community. The research is dedicated to bridging the Digital Divide. The objectives includes (i) building a low cost server using off-the-shelf, low cost hardware and open source software (ii) Provide a high speed data communications network effectively creating a Local Area Network (iii) Run the entire system on an incredibly low power requirement of 3.5 Watts. (iv) Provide a service layer for web services which supports Ajax, php5, MySQL (v) Deploy open source web services for data exchange and communication (vi) provide a system that has low & quick maintenance capabilities, (vii) and finally allow optional cellular (3G) data connectivity to allow the people to have shared internet access.

With the rapid development and advances of very large scale integration technology and wafer-scale integration technology, multiprocessor systems, taking interconnection networks as underlying topologies, have been widely designed and used in big data era. The topology of an interconnection network is usually represented as a graph. If any two distinct vertices [Formula: see text] in a connected graph [Formula: see text] are connected by min[Formula: see text] vertex (edge)-disjoint paths, then [Formula: see text] is called strongly Menger (edge) connected. In 1996, Opatrny et al. [16] introduced the DCC (Disjoint Consecutive Cycle) linear congruential graph, which consists of [Formula: see text] nodes and is generated by a set of linear functions [Formula: see text] with special properties. In this work, we investigate the strong Menger connectivity of the DCC linear congruential graph [Formula: see text] with faulty vertices or edges, where [Formula: see text], [Formula: see text], gcd[Formula: see text] and [Formula: see text] is a multiple of [Formula: see text]. In detail, we show that [Formula: see text] is strongly Menger connected if [Formula: see text] for any [Formula: see text]. Moreover, we determine that [Formula: see text] is strongly Menger edge connected if [Formula: see text] for any [Formula: see text]. Furthermore, we prove that, under the restricted condition [Formula: see text], [Formula: see text] is strongly Menger edge connected if [Formula: see text] and [Formula: see text] for any [Formula: see text]. In addition, we present some empirical examples to show that the bounds are all optimal in the sense of the maximum number of tolerable edge faults.

GROM: A generalized routing optimization method with graph neural network and deep reinforcement learning