Execution-time Prediction for Dynamic Streaming Applications with Task-level Parallelism

Streaming applications are promising targets for effectively utilizing multicores because of their inherent amenability to pipelined parallelism. While existing methods of orchestrating streaming programs on multicores have mostly been static, real-world applications show ample variations in execution time that may cause the achieved speedup and throughput to be sub-optimal. One of the principle challenges for moving towards dynamic orchestration has been the lack of approaches that can predict or accurately estimate upcoming dynamic variations in execution efficiently, well before they occur. In this paper, we propose an automated dynamic execution behavior prediction approach that can be used to efficiently estimate the time that will be spent in different pipeline stages for upcoming inputs without requiring program execution. This enables dynamic balancing or scheduling of execution to achieve better speedup. Our approach first uses dynamic taint analysis to automatically generates an input-based execution characterization of the streaming program, which identifies the key control points where variation in execution might occur with the associated input elements that cause these variations.We then automatically generate a light-weight emulator from the program using this characterization that can simulate the execution paths taken for new streaming inputs and provide an estimate of execution time that will be spent in processing these inputs, enabling prediction of possible dynamic variations. We present experimental evidence that our technique can accurately and efficiently estimate execution behaviors for several benchmarks. Our experiments show that dynamic orchestration using our predicted execution behavior can achieve considerably higher speedup than static orchestration.

With the advent of multi-core processors, parallel execution of multiple tasks has become a common practice. Various scheduling algorithms have addressed this issue considering multiprocessor systems. Most of these algorithms target application level parallelism. Task level parallelism within an application can be exploited using shared memory architecture such as multi-core processor or in a distributed computing environment. In this paper, we propose a static scheduling algorithm that generates a schedule that can be optimized for one or all parameters including execution time, number of processors, and efficiency of processors. The input to this scheduler is a task dependency matrix is generated using dependency analysis technique. Efficiency of this scheduler is high because it uses multiple parameters such as task wait time, number of tasks whose dependency gets resolved by scheduling a task, and task execution time. The paper concludes with an example of applying this technique to a set of tasks.

Energy consumption reduction is today an important design issue for all kinds of digital systems. Offering both flexibility and efficient energy management, variable speed processor architectures are preferred for low energy consumption even in hard real-time systems. For this type of system, the main approach consists in trading speed for lower energy while meeting all deadlines. For tasks with varying execution time, speed scheduling is most efficient if performed at run-time. This paper presents a new ordering technique for such tasks, that reduces the energy consumption resulting from the run-time speed scheduling. Without affecting the real-time behavior, our uncertainty-based scheduling (UBS) is a low complexity but energy-efficient method that can be applied on top of already existent real-time scheduling techniques, such as EDF. These claims are backed up by extensive simulation results accompanied by measurements on a platform based on an Intel i80200 XScale processor.

In computer experiments, many research works rely on the accuracy of measured programs' execution time. We observe that not all studies consider that repeated executions of the same program, under the same experimental conditions, may produce statistically significant different completion times. In this work, we experimentally demonstrate that several sources of OS Jitter affect the execution time of computer programs. We compare various execution time samples using three test protocols, which apply different statistical techniques. The results show that significant differences are detected in all evaluated scenarios.

Traditional hard real-time scheduling algorithms require the use of the worst-case execution times to guarantee that deadlines will be met. Unfortunately, many algorithms with parameters derived from sensing the physical world suffer large variations in execution time, leading to pessimistic overall utilization, such as visual recognition tasks. In this article, we present ZS-QRAM, a scheduling approach that enables the use of flexible execution times and application-derived utility to tasks in order to maximize total system utility. In particular, we provide a detailed description of the algorithm, the formal proofs for its temporal protection, and a detailed, evaluation. Our evaluation uses the Utility Degradation Resilience (UDR) showing that ZS-QRAM is able to obtain 4× as much UDR as ZSRM, a previous overbooking approach, and almost 2× as much UDR as Rate-Monotonic with Period Transformation (RM/TP). We then evaluate a Linux kernel module implementation of our scheduler on an Unmanned Air Vehicle (UAV) platform. We show that, by using our approach, we are able to keep the tasks that render the most utility by degrading lower-utility ones even in the presence of highly dynamic execution times.

Minor variations in execution time can lead to out-sized effects on the behavior of an application as a whole. There are many sources of such variation within modern multi-core computer systems. For an otherwise deterministic application, we would expect the execution time variation to be non-existent (effectively zero). Unfortunately, this expectation is in error. For instance, variance in the realized execution time tends to increase as the number of processes per compute core increases. Recognizing that characterizing the exact variation or the maximal variation might be a futile task, we take a different approach, focusing instead on the best case variation. We propose a modified (truncated) Levy distribution to characterize this variation. Using empirical sampling we also derive a model to parametrize this distribution that doesn’t require expensive distribution fitting, relying only on known parameters of the system. The distributional assumptions and parametrization model are evaluated on multi-core systems with the common Linux completely fair scheduler.

Providing high-quality broadcast services for soft real-time applications over wireless networks such as CDMA2000, which have high bit error rates, requires the control of errors that occur during data transmission. Reed-Solomon (RS) forward error correction (FEC) in the medium access control (MAC) layer performs this role in 3G broadcast services. We propose new analytic models for predicting the performance of RS coding and its execution time, which take into account the memory property of a fading channel, different channel conditions, and a variable level of block interleaving. We identify RS decoding as a significant cause of variability in execution time, taking the form of jitter, which depends on the channel conditions. We analyze the size of buffer required to absorb the jitter under different channel conditions. We then formulate a trade-off between the performance of RS coding and the delay that it causes in transmitting a fixed amount of data with different levels of block interleaving. Finally, we show how to balance the quality with which content is presented against an acceptable buffering delay, which is very important to soft real-time applications, by using an adequate level of block interleaving. This study offers a guide for the provision of efficient broadcast services in real time with stochastically guaranteed quality.

Multimedia applications are an increasingly important workload for general-purpose processors. This paper analyzes frame-level execution time variability for several multimedia applications on general-purpose architectures. There are two reasons for such an analysis. First, it has been conjectured that complex features of such architectures (e.g., out-of-order issue) result in unpredictable execution times, making them unsuitable for meeting real-time requirements of multimedia applications. Our analysis tests this conjecture. Second, such an analysis can be used to effectively employ recently proposed adaptive architectures.

EDF (Earliest Deadline First) has been proved to be optimal scheduling algorithm for single processor real-time system. It also performs well for multiprocessor system. Limitation of EDF is that its performance decreases exponentially when system becomes slightly overloaded. ACO (Ant Colony Optimization) based scheduling algorithm performs well in both underloaded and overloaded conditions. But its limitation is that it takes more time for execution compared to EDF. In this paper, an adaptive algorithm for multiprocessor real-time system is proposed, which is combination of both of these algorithms. The proposed algorithm along with EDF and ACO based algorithm is simulated for real-time multiprocessor system and the results are obtained. The performance is measured in terms of Success Ratio (SR) and Effective CPU Utilization (ECU). Execution Time taken by each scheduling algorithm is also measured. From analysis and experiments, it reveals that the proposed algorithm is fast as well as efficient in both underloaded and overloaded conditions for real-time multiprocessor systems.

Dynamic Voltage Scaling (DVS) is one of the techniques used to obtain energy-saving in real-time DSP systems. In many DSP systems, some tasks contain conditional instructions that have different execution times for different inputs. Due to the uncertainties in execution time of these tasks, this paper models each varied execution time as a probabilistic random variable and solves the Voltage Assignment with Probability (VAP) Problem. VAP problem involves finding a voltage level to be used for each node of an date flow graph (DFG) in uniprocessor and multiprocessor DSP systems. This paper proposes two optimal algorithms, one for uniprocessor and one for multiprocessor DSP systems, to minimize the expected total energy consumption while satisfying the timing constraint with a guaranteed confidence probability. The experimental results show that our approach achieves significant energy saving than previous work. For example, our algorithm for multiprocessor achieves an average improvement of 56.1% on total energy-saving with 0.80 probability satisfying timing constraint.

In this paper, processor scheduling policies that "save" processors are introduced and studied. In a multiprogrammed parallel system, a "processor saving" scheduling policy purposefully keeps some of the available processors idle in the presence of work to be done. The conditions under which processor saving policies can be more effective than their greedy counterparts, i.e., policies that never leave processors idle in the presence of work to be done, are examined. Sensitivity analysis is performed with respect to application speedup, system size, coefficient of variation of the applications' execution time, variability in the arrival process, and multiclass workloads. Analytical, simulation, and experimental results show that processor saving policies outperform their greedy counterparts under a variety of system and workload characteristics.

Embedded multiprocessor systems are often used in the domain of real-time stream processing applications to keep up with increasing power and performance requirements. Examples of such real-time stream processing applications are digital radio baseband processing and WLAN transceivers. These stream processing applications often have a dynamic character. For example the execution times and execution rates of the tasks of the stream processing applications vary and can even be data dependent. To cope with this dynamic behavior, the tasks are executed on the multiprocessor system in a data-driven fashion on run-time scheduled resources. Another important aspect of real-time stream processing applications are their strict performance constraints. A periodic source or sink imposes a throughput constraint and also latency constraints are common. For stream processing applications, violating these constraints typically leads to a major reduction of the quality of service of the applications. To prevent such violations of the temporal constraints, analysis methods are used. These analysis methods ease the processes of dimensioning, programming and optimizing the multiprocessor systems within these temporal constraints. Analysis methods rely on accurate abstractions of the analyzed applications. However, current abstractions have a limited accuracy and applicability and do therefore not always suffice. In this thesis we will present abstractions for multiprocessor systems in which the tasks are executed in a data-driven fashion and in which they have aperiodic schedules. These aperiodic schedules can capture the dynamic behavior of the real-time stream processing applications. We present accurate abstractions based on dataflow analysis techniques which can be used for a large class of multiprocessor systems. Compared to state of the art, we broaden the scope of dataflow analysis techniques, improve their accuracy and provide a new higher level of abstraction.

This paper proposes a solution to air traffic control (ATC) using an enhanced SIMD machine model called an Associative Processor (AP). Our solution differs from previous ATC systems that are designed for MIMD computers and have a great deal of difficulty meeting the predictability requirements for ATC, which are critical for meeting the strict certification standards required for safety critical software components. The proposed AP solution supports accurate predictions of worst case execution times and guarantees all deadlines are met. Furthermore, the software developed based on the AP model is much simpler and smaller in size than the current corresponding ATC software. As the associative processor is built from SIMD hardware, it is considerably cheaper and simpler than the MIMD hardware currently used to support ATC. We have designed a prototype for eight ATC real-time tasks on Clear Speed CSX600 accelerator that is used to emulate AP. Performance is evaluated in terms of execution time and predictability and is compared to the fastest host-only version implemented using OpenMP on an 8-core multiprocessor (MIMD). Our extensive experiments show that the AP implementation meets all deadlines that can be statically scheduled. To the contrary, some tasks miss their deadlines when implemented on MIMD. It is shown that the proposed AP solution will support accurate and meaningful predictions of worst case execution times and will guarantee that all deadlines are met.

The exponential growth of genomic and omics data has necessitated scalable, reproducible, and efficient computational frameworks. This study investigates the role of bioinformatics pipelines within marketplace ecosystems, focusing on their impact on data-driven genomic and biotech analytics. By evaluating multiple pipeline modules across pre-processing, analysis, and annotation stages, the findings reveal significant variation in execution time, memory utilization, accuracy, and reproducibility. Comparative assessment of marketplaces such as DNAnexus, Seven Bridges, and Galaxy demonstrates that technical interoperability, containerization efficiency, and regulatory compliance are critical drivers of adoption, while cost structures remain a major determinant for user segmentation. Machine learning integration within pipelines substantially enhanced predictive modeling for biomarker detection and drug-target prediction, with deep learning and random forest models achieving the strongest performance. Multivariate statistical analyses confirmed that interoperability and compliance positively influence adoption rates, whereas higher costs act as a barrier. Dimensionality reduction through PCA enabled effective cohort stratification, while cluster analysis identified distinct marketplace adoption patterns, emphasizing the heterogeneity of user needs. Overall, the study underscores the transformative potential of integrating pipelines with marketplace infrastructures, enabling scalable biotech innovation, democratizing access to advanced tools, and advancing precision medicine.

Over the last decade the relative latency of access to shared memory by multicore increased as wire resistance dominated latency and low wire density layout pushed multi-port memories farther away from their ports. Various techniques were deployed to improve average memory access latencies, such as speculative pre-fetching and branch-prediction, often leading to high variance in execution time which is unacceptable in real-time systems. Smart DMAs can be used to directly copy data into a layer-1 SRAM, but with overhead. The VLIW architecture, the de-facto signal-processing engine, suffers badly from a breakdown in lock-step execution of scalar and vector instructions. We describe the Split Latency Adaptive Pipeline (SLAP) VLIW architecture, a cache performance improvement technology that requires zero change to object code, while removing smart DMAs and their overhead. SLAP builds on the Decoupled Access and Execute concept by 1) breaking lock-step execution of functional units, 2) enabling variable vector length for variable data-level parallelism, and 3) adding a novel triangular-load mechanism. We discuss the SLAP architecture and demonstrate the performance benefits on real traces from a wireless baseband-system (where even the most compute intensive functions suffer from an Amdahl’s law limitation due to a mixture of scalar and vector processing).