Exploring power management in multi-core systems

This paper presents an integrated power management unit (PMU) to improve the power and area efficiencies of the transcutaneous power transmission in biomedical implants. An auto-reconfigurable multi-ratio SC DC-DC regulator is developed within the PMU not only to maintain high system power efficiency under coupling variations but also to reduce the number of required capacitors and power transistors in the system. Implemented in a 0.35-μm CMOS process, the PMU can take an AC input with the signal amplitude of 1.9 V - 3.5 V and provide a regulated output voltage of 4 V. Simulation results show that the proposed PMU can deliver a maximum output current of 10 mA and achieve the peak power efficiency of 83%.

Several novel digital assistant power integrated technologies (DAPITs) for power management unit (PMU) to reduce the designing complexity, as well as to keep good performance in scaling CMOS process, are proposed in this paper. The DAPITs include segment power driving with pulse skip modulation/pulse width modulation and loop regulating with digital regulation circuit for dc-dcs in PMU, calibrating digital-to-analog converter (DAC) with resistance compensation network for dynamic voltage scaling (DVS), and separating phase clock for multi-dc-dcs in PMU. With these DAPITs, the efficiencies and output accuracies of dc-dcs are increased, the DVS signal sent by DAC is linear, and current ripples in PMU are reduced. In this paper, a PMU embedded into system-on-a-chip (SoC) is designed based on a 0.13-μm CMOS process. The designed PMU includes four dc-dc buck converters and two LDOs. This paper introduces the top structure of the PMU and the main proposed DAPITs. Simulation and test results show that the output voltages of the dc-dc converters in the PMU can be changed by external resistors and regulated from 0.7 to 1.8 V stepped with 25 mV by SoC load through interface. And the maximum efficiency of the dc-dcs with DVS in the PMU is more than 90%, while, with an external resistor, it can reach to 95%.

A highly integrated power management unit (PMU) with dual DVS-enabled regulators is proposed in this paper. The PMU provides four buck regulators and two low dropout regulators, in which there are two DVS-enabled buck regulators. The output voltages can be optimized separately in the applications with two adaptive voltage domains. The PMU with dual DVS-enabled regulators provides high efficiency and convenient solution for portable devices. The voltage and current references are distributed by considering substrate noise from switching regulators. Interleaving operation of switching regulators minimizes input current ripple. Floating ground is generated in the control block of switching regulators by voltage buffer to further improve the negative power supply rejection (PSR?). The PMU is designed and fabricated with 0.13 μm CMOS process and occupies 5.29 mm2 active silicon area. Experimental results show that the PMU provides good isolation between channels and the DVS speeds for 250 mA ILoad are 63.6 and 45.5 μs/V when up-tracking and down-tracking, respectively. The proposed PMU can be embedded in low power SoCs, facilitating the DVFS scheme for multiple voltage domains.

This article presents a power management unit (PMU) enabling ultra-wide power-performance tradeoff well beyond voltage scaling, and adaptation to the sensed power/energy availability in the harvester and battery. Gap-less power scaling by more than five orders of magnitude and down to nW permits continuous microcontroller unit (MCU) operation regardless of the battery energy availability, thanks to a sub-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> on-chip harvester. Such battery-indifferent operation allows to considerably shrink the battery down, as battery discharge no longer has disruptive impact on operation. Battery-indifferent operation is enabled by introducing a purely harvested power mode in the PMU, and widely power-scalable circuits in critical blocks to maintain the power efficiency nearly constant down to nW level. To avoid pessimistic power/timing overdesign, a novel self-biasing comparator and a zero current switching scheme with fast convergence and circuit sharing across power modes are proposed. A 180-nm testchip shows MSP430-like MCU power scaling from sub-mW down to 1.85 nW, with at least 27× power dynamic range extension compared to prior art. Self-start-up from 2-nW harvested power is demonstrated, corresponding to a 0.8-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> on-chip solar cell with 100-lx illuminance (i.e., equivalent to a very dark overcast day).

Power dissipation has become a critical design constraint for the growth of modern multicore systems due to increasing clock frequencies, leakage currents, and system parasitics. To overcome this urgent crisis, this article presents an embedded platform for on-chip power management of a multicore System-on-Chip (SoC). The design involves the development of two key components, from the hardware to the software level. From the hardware perspective, a multiple-supply power management unit is proposed and is implemented using a Single-Inductor Multiple-Output (SIMO) DC-DC converter. To dynamically respond to the sensed instantaneous power demands and to accurately control the power delivery to the processor cores, the power management unit employs a software-defined adaptive global/local power allocation feedback controller. The proposed controller is designed using the hardware-software codesign methodology to uniquely control the SIMO converter during various operation scenarios. This is achieved using several embedded software control algorithms that operate synergetically to ensure efficient and reliable system operation. The hardware-software codesign technique also allows the SIMO controller to be integrated with future microprocessor cores. Therefore, by employing the vast amount of on-chip resources, the converter can perform effective power processing to provide the most power-optimal voltages at the hardware level. Such an embedded power management module leads to an integrated, power-aware, and autonomous SoC design that is independent of additional external hardware control, thereby reducing on-chip area and system complexity. In this design, each power output from the SIMO converter provides a step-up/down voltage conversion, thereby enabling a wide range of variable supply voltage. An adaptive global/local power allocation control algorithm is employed to significantly improve Dynamic Voltage and Frequency Scaling (DVFS) tracking speed and line/load regulation, while still retaining low cross-regulation. Designed with a 180nm CMOS process, the converter precisely provides three independently variable power outputs from 0.9 V to 3.0 V, with a total power range from 33 mW to 900 mW. A very fast load transient response of 3.25 μ s is achieved, in response to a 67.5-mA full-step load current change. The design thus provides a cost-effective power management solution to achieve a robust, fast-transient, DVFS-compatible multicore SoC.

A power management unit (PMU) with battery extender and output load regulation is presented using 0.18$\mu$m CMOS technology. For designing few sub-circuits of the PMU, subthreshold region of MOSFET is utilized, which significantly contributes to achieve low power operation. The proposed PMU consists of a voltage regulator, a voltage monitor, a battery backup module and two DC-DC Switched Capacitor (SC) Converters. The regulator output voltage V OUT is regulated at 0.95 V and 0.968 V at input voltages of 0.98 V and 1.33 V respectively. To ensure continuous operation at the load circuit, a battery extender module is implemented in case of unavailability of EH source. The power consumption of the PMU at input voltages of 0.98 V and 1.33 V is 46nW and 1.567 $\mu$W respectively. Near threshold operation is ensured at the load side by further regulating the voltage at the output to 0.67 V and 0.5 V using 3:2 and 2:1 SC Converters respectively. The current consumption of the 3:2 and 2:1 SC Converters is 748 nA and 751 nA respectively. The proposed PMU can deliver output current up to 1 mA at 1.33 V of input voltage and is suitable for numerous applications where low power operation is essential as it consumes a small amount of power.

With the rapid development of smart grid technology, more and more attention has been paid to the stability of the power grid. When the power grid fails, the dispatch center will receive various types of data, including the PMU data collected by the PMU (Power Management Unit) device used by the Wide Area Monitoring System (WAMS) and the data collected by the Supervisory Control System for Data Acquisition and Control (SCADA). Alarm information data, they describe the same grid fault from different dimensions. At present, the power grid fault diagnosis based on PMU data and alarm information texts has been fully studied, but the information source is single, and it is difficult to ensure the accuracy of the diagnosis results when complex faults and multiple faults occur in the power grid. This paper starts with the information source of power grid fault diagnosis and develops a power grid fault diagnosis method that integrates the dual data sources of PMU and alarm information: 1. effectively connect alarm message text and PMU based on fault events. 2. complete the fusion of PMU and alarm information to improve the scope and accuracy of power grid fault diagnosis. Finally, the simulation fault data is used to test. The experimental results show that the accuracy of fault diagnosis of dual data source fusion is higher than that of single data.

Portable wireless systems require long battery lifetime while still delivering high performance. The major contribution of this work is combining new it power management(PM) and it power control (PC) algorithms to trade off performance for power consumption at the system level in portable devices. First we present the formulation for the solution of the PM policy optimization based on renewaltheory. Next we present the formulation for power control (PC) of the wireless link that enables us to obtain further energy savings when thesystem is active. Finally, we discuss the measurements obtained for a set of PM and PC algorithms implemented for the WLAN card on a laptop. The PM policy we developed based on our renewal model consumes three times less power as compared to the default PM policy for the WLAN card with still high performance. Power control saves additional 53% in energy at same bit error rate. With both power control and power management algorithms in place, we observe on average a factor of six in power savings.

This two-part paper reviews recent innovations in circuit design that have accelerated the miniaturization of sensor nodes. In this second part of the paper, we focus on key building blocks of miniaturized sensor nodes, such as data transceivers, energy harvesters, power management units, and digital logic circuits. System level design considerations are also discussed to provide guidelines for the design of a miniaturized system. As an example prototype design, a 2.7-cm3 global navigation satellite system (GNSS) logger is proposed. This paper includes a die-stacked sensor platform composed of an ARM cortex M0 processor, energy harvester, power management unit, solar cell, optical receiver, sensor layer, and RF transmitter that exploits the discussed design techniques for ultra-low power operation. The GNSS logger can store GNSS signals of >1 k positions on a single battery charging without additional energy harvesting.

The future looks bright for power management in mobile phones. Experiencing dynamic growth, power management units - with a range of integration levels - have recently flooded the, market. While no obvious trend for these levels of integration has yet emerged, one fact is clear. As consumers demand more and more applications in their wireless handsets, power management integration will be key The power section in a mobile phone is reasonably simple. It consists of an array of low power linear regulators and amplifiers. The complexity comes from managing these functions, which requires the additional integration of digital blocks such as a system management bus for serial communication, microcontrollers for correct power sequencing as well as reliable on-board data conversion.

This letter presents a RISC-V System-on-Chip (SoC) with fully integrated switched-capacitor DC–DC converters, adaptive clock generators, mixed-precision floating-point vector accelerators, a 5-Gb/s serial memory interface, and an integrated power management unit (PMU) manufactured in 28-nm FD-SOI. The vector accelerator improves performance and energy per task on a matrix multiplication kernel by 15x and 13x, respectively, and end-to-end performance on machine learning and graph analytical workloads by 8x–12x. Inclusion of microarchitectural counters and fine spatial power-domain granularity facilitate the predictive power-management algorithms that reduce energy per task by 13%–22% compared to the baseline scalar processor. System level simulations of a range of SoC architectural variations with multiple cores and vector accelerators complement the silicon measurements.

Dynamic power management features are now an integral part of processor chip and system design. Dynamic voltage and frequency scaling (DVFS), core folding and per-core power gating (PCPG) are power control actuators (or knobs) that are available in modern multi-core systems. However, figuring out the actuation protocol for such knobs in order to achieve maximum efficiency has so far remained an open research problem. In the context of specific system utilization dynamics, the desirable order of applying these knobs is not easy to determine. For complexity-effective algorithm development, DVFS, core folding and PCPG control methods have evolved in a somewhat decoupled manner. However, as we show in this paper, independent actuation of these techniques can lead to conflicting decisions that jeopardize the system in terms of power-performance efficiency. Therefore, a more robust coordination protocol is necessary in orchestrating the power management functions. Heuristics for achieving such coordinated control are already becoming available in server systems. It remains an open research problem to optimally adjust power and performance management options at runtime for a wide range of time-varying workload applications, environmental conditions, and power constraints. This research paper contributes a novel approach for a systematically architected, robust, multi-knob power management protocol, which we empirically analyze on live server systems. We use a latest generation POWER7+ multi-core system to demonstrate the benefits of our proposed new coordinated power management algorithm (called PAMPA). We report measurement-based analysis to show that PAMPA achieves comparable power-performance efficiencies (relative to a baseline decoupled control system) while achieving conflict-free actuation and robust operation.

Battery-less active implantable devices are of interest because they offer longer life span and eliminate costly battery replacement surgical interventions. This is possible as a result of advances in inductive power transfer and development of power management circuits to maximize the overall power transfer and provide various voltage levels for multi-functional implantable devices. Rehabilitation therapy using optical stimulation of genetically modified peripheral neurons requires high current loads. Standard rectification topologies are inefficient and have associated voltage drops unsuited for miniaturized implants. This paper presents an integrated power management unit (PMU) for an optical-electrical stimulator to be used in the treatment of motor neurone disease. It includes a power-efficient regulating rectifier with a novel body biased high-speed comparator providing 3.3 V for the operation of the stimulator, a 3-stage latch-up charge pump with 12 V output for the input stage of the optical-electrical stimulator, and 1.8 V for digital control logic. The chip was fabricated in a 0.18 lm CMOS process. Measured results show that for a regulated output of 3.3 V delivering 30.3 mW power, the peak power conversion efficiency is 84.2% at 6.78 MHz inductive link tunable frequency reducing to 70.3% at 13.56 MHz. The charge pump with on chip capacitors has 90.9% measured voltage conversion efficiency.

Power management becomes an integral part of hardware-systems design. In modern complex systems, the powermanagement design is not a simple task and it is quite difficult to evaluate whether the designed strategy is the best. In this paper, we propose a new method for overhead estimation of the required power-management unit, based on system-level abstract specification. It enables a designer to explore various power-management strategies in a short time and select the most suitable one. It is especially useful for ultra low-power systems, in which the power-management unit is a significant power consumer. The proposed method is simpler and faster than the existing approaches, and thus it speeds-up the low-power systems development process.

Power Management Units (PMU) are rapidly being developed to provide a significant amount of power for sensors in Internet-of-Things (IoT) networks. This paper presents a novel optimized PMU design for IoT applications, which can be used as a part of energy harvesting system that can be composed of solar cells, wind turbine, thermal energy, and vibration. Hence the proposed design can be used as a feasible energy harvester, where notable power efficiency is achieved here over traditional PMU designs under the same circumstances. The optimized PMU is developed using a buck-boost DC-DC converter. The particle swarm optimization (PSO) is then applied to optimize the parameters of PMU, including buck-boost DC-DC converter, and control circuitry to achieve maximum power point and improve the overall efficiency.