Extensible and Configurable RISC-V Based Virtual Prototype

Internet-of-Things (IoT) opens a new world of possibilities for both personal and industrial applications. At the heart of an IoT device, the processor is the core component. Hence, as an open and free instruction set architecture RISC-V is gaining huge popularity for IoT. A large ecosystem is available around RISC-V, including various RTL implementations at one end and high-speed instruction set simulators (ISSs) at the other end. These ISSs facilitate functional verification of RTL implementations as well as early SW development to some extent. However, being designed predominantly for speed, they can hardly be extended to support further system-level use cases such as design space exploration, power/timing/performance validation or analysis of complex HW/SW interactions. In this paper, we propose and implement the first RISC-V based Virtual Prototype (VP) with the goal of filling this gap. We provide a RISC-V RV321M core, a PLIC-based interrupt controller and an essential set of peripherals together with SW debug capabilities. The VP is designed as extensible and configurable platform with a generic bus system and implemented in standard-compliant SystemC and TLM-2.0. The latter point is very important, since it allows to leverage cutting-edge SystemC-based modeling techniques needed for the mentioned use cases. Our VP allows a significantly faster simulation compared to RTL, while being more accurate than existing ISSs. Finally, our RISC-V VP is fully open source to help expanding the RISC-V ecosystem and stimulating further research and development.

Recently, Virtual Prototypes (VPs) were introduced for the emerging RISC-V Instruction Set Architecture (ISA) and become an important part of the growing RISC-V ecosystem. A central component of the VP is the Instruction Set Simulator (ISS). VPs should provide a high simulation performance and at the same time yield accurate results, which are two conflicting requirements. To tackle this problem, we present an efficient VP-based adaptive simulation that is tailored for the RISC-V ISA and allows to seamlessly switch the accuracy setting in the ISS at runtime. This enables to selectively simulate the application as fast as possible and as accurate as necessary. In this paper we focus on the performance impact of different accuracy settings and leave the evaluation of accuracy results for future work. Our RISC-V experiments, using bare-metal and operating system based benchmarks, demonstrate that up-to 543x speed-up is possible with a JIT-based setting in the ISS.

This chapter discusses the challenges of creating an instruction set simulator (ISS) and system modeling environment for configurable, extensible processors. Processor generation technology is highly automated and is used by designers to create application-specific instruction set processors (ASIPs) targeted to specific application domains. The main challenges for creating an ISS lie in the configurable and extensible nature of the processor, which is tailored by designers at design time, not fixed in advance. Thus simulation models need to be created on the fly when designers have configured a new version of the processor. They need to be created automatically and offer good performance with a variety of use modes. In addition, multiple speed-accuracy trade-offs are necessary to support these various use modes, such as instruction-accurate, cycle-accurate, and pin-level. Furthermore, these ISS models must themselves fit into system modeling and simulation environments, both generated along with the ASIP and commercial third party ESL/EDA tools. Again, multiple use models and trade-offs in simulation scope, speed, and accuracy must be supported. Standards to ease integration and model interoperability in this area have arrived only recently and are just beginning to make life easier for model providers.

This paper presents BURAQ, a DSP development framework, which aims at optimizing cost, efficiency and turn around time of system-on-chip development. BURAQ accepts an instruction and architecture description (IAD) file that represents the DSP and its instruction set at a higher level of abstraction, in a proprietary language. The system then synthesizes a complete hardware description of the processor core, along with accompanying tools i.e. ILP assembler, linker and instruction set simulator. The synthesized processor core is composed of a processor kernel, registers, addressing units and functional units. A user friendly IDE for the above mentioned framework has also been developed and it allows easy specification and detailed analysis of the target architecture. Hence BURAQ allows a platform for hardware/software co-simulation of a DSP. co-simulation is a very powerful tool for early design space exploration and thus reducing production cost and development time of SOC architectures. The effectiveness of BURAQ was verified with a successful modeling of Texas Instruments' TMS320C6x and StarCore's SC140.

This paper describes an on-line memory and CPU register state validation methodology in virtualized simulated environments where an Instruction Set Simulator (ISS) executes native applications on top of Operating System (OS) and dynamic translation is enabled. A Virtual System Prototyping (VSP) environment models a platform providing host memory pointers and a CPU core requesting read, write and execute direct memory accesses to the platform. A platform allocated shadow memory captures memory accesses during native code instruction execution. Another specially cloned shadow memory copy that supplies host pointers to the core captures memory accesses while executing dynamically translated code instructions. The methodology comprises saving execution contexts, reloading the ISS from a restart point and brunching the ISS execution either on native or translated codes. An online checker compares memory and register states at specially defined check points of interest. A cosimulation tool has been implemented in C++ as a loadable module into the VSP controlled by the ISS simulated events.

RISC-V is a modern open source Instruction Set Architecture (ISA) and designed in a very extendable manner, which allows for highly application specific solutions. However, the identification of suitable instruction set extensions usually requires a significant manual effort and therefore is a very challenging process. In this paper we propose a lightweight alternative methodology to find suitable application-specific RISC-V extensions, using a Virtual Prototype (VP). This is done, purely by observing the used instructions during the execution of the targeted application on the VP. Therefore, no further information about the application itself are needed. In this context the advantages and the flexibility of a VP and the straightforward extendability of the RISC-V ISA are demonstrated.

Instruction Set Simulators (ISSes) are important tools for cross-platform software development. The simulation speed is a major concern and many approaches have been proposed to improve the performance of ISSes. A prevalent technique is compiled simulation, which translates target programs into host instructions. But orders of magnitude of speed deterioration is inevitable since the difference between target and host Instruction Set Architectures (ISAs) can be large. An alternative is to emulate the program without sticking to binary compatibility. The performance problem is solved by using native execution. However, these emulators either require a special programming language, or a given Application Programming Interface (API). Last but not least, it is not trivial to integrate an emulator into a system simulator (which provides devices, external memory, etc., that the embedded programmers do care). In this paper, we propose a fast and generic hybrid simulation approach using virtualization technique to accelerate simulation and simulator-based debugging of C programs. A novel virtual coprocessor (VCP) is introduced as a processing element which executes C functions at high speed. This approach is C89 compliant and compatible with third party libraries and platform dependent code. It is also retargetable and can be integrated with existing ISSes. Two different ISAs are supported at present: MIPS and mAgic DSP. The average execution speed of the coprocessor is about 100 million simulated instructions per second.

Fast estimation of processor performance can easily lead to large savings in time which would otherwise be spent in long time consuming execution on an instruction set simulator. The estimation of standard library functions are made difficult by the fact that standard libraries are sometimes delivered as binary files, which makes use of an instruction set simulator, the only option for performance estimation. In this paper, we present an estimation methodology which does not require execution of an application on an instruction set simulator. We use simple mathematical model of performance of standard library function which relates the number of instruction executed to the size/number of arguments passed.

In recent years multi-core processors have seen broad adoption in application domains ranging from embedded systems through general-purpose computing to large-scale data centres. Simulation technology for multi-core systems, however, lags behind and does not provide the simulation speed required to effectively support design space exploration and parallel software development. While state-of-the-art instruction set simulators (Iss) for single-core machines reach or exceed the performance levels of speed-optimised silicon implementations of embedded processors, the same does not hold for multi-core simulators where large performance penalties are to be paid. In this paper we develop a fast and scalable simulation methodology for multi-core platforms based on parallel and just-in-time (Jit) dynamic binary translation (Dbt). Our approach can model large-scale multi-core configurations, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded multi-core platform implementing the ARCompact instruction set architecture (Isa). We have evaluated our parallel simulation methodology against the industry standard Splash-2 and Eembc MultiBench benchmarks and demonstrate simulation speeds up to 25,307 Mips on a 32-core x86 host machine for as many as 2,048 target processors whilst exhibiting minimal and near constant overhead, including memory considerations.

This paper predicts programspsila effect of time-domain electromagnetic interference (EMI) on a simple microcontroller. Using the instruction current concept and a modified instruction set simulator (ISS) for this purpose, this paper can predict, in the time domain, accurate conducted EMI behaviors when different programs are running on this system. Different program codespsila EMI behaviors are predicted, and all of these codes fit well with the measurement results. The modified ISS is adapted to estimate the pipeline effect of a microcontroller and to give an accurate current profile of any complex multi-instruction program. By using the instruction current model and the proposed ISS, this paper can predict the EMI behavior of a very complex program-a simple home-made operating system (OS) kernel. To the best of our knowledge, this paper is the first work on observation and prediction of EMI behavior of an embedded system OS kernel.

In this work, we present an exploration platform for microcoded RISC-V cores leveraging the One Instruction Set Computer (OISC) principle. Following the industry-proven virtual prototyping approach, we have realized our exploration platform by implementing an extensible and configurable Instruction Set Simulator (ISS). The developed ORISCV-ISS combines the advanced ecosystem of RISC-V with the ultimate minimalism of OISCs. ORISCV-ISS serves as development platform for both, hardware architecture and microcode procedures, and provides the basis for early design space exploration. Using ORISCV-ISS, we developed SUBLEQ microcode that is fully RISC-V compliant and ready to be run on real hardware. We evaluate how multiple hardware configurations and OISC extensions affect the performance, providing key information to balance between area savings and system performance.

The advancing automation of the industrial production requires faster and more efficient programmable logic controllers. Today's controller architectures based on specialized processors to execute the STL application are at their limits. For any further improvement the architecture of these processors needs to evolve from single core in order execution to a multicore out of order architecture. This step can not occur without additions to the PLC's instruction set. Therefore a PLC processor instruction set simulation is required that allows a quick evaluation of the effectiveness and efficiency of instruction set changes as well as changes to the processor's architecture. Current architecture description languages (ADL) allow the fast modeling of these changes with enough flexibility for the planned improvements and provide fast simulation speed. This work presents for the first time an instruction set simulation environment for STL compatible PLC processors using the ADL ArchC as a base for further research.

Instruction set simulators (ISS) are indispensable tools for the development of new architectures and embedded software. One essential part of any ISS is its instruction decoder. Since manual implementation of an instruction decoder for a complex instruction set is tedious and error-prone, automatic generation of an instruction decoder is required. However, as a result of the increasing irregularity of instruction encoding because of the incremental addition of instructions, generating efficient instruction decoders is complicated. In this paper, we propose a generation algorithm of a decision tree for decoding irregular instructions. Our algorithm can generate decision trees by using not only significant bits of opcode patterns but also exclusion conditions in decoding entries. Our results on ARMv7, Thumb-2, MIPS64, RH850, and TriCore show that our algorithm generates efficient instruction decoders in terms of both depth and memory consumption regardless of whether the target instruction set is irregular or not.

International audience

Today, parts of an ESL model can be automatically synthesized to a low-level implementation, e. g., via high-level synthesis. However, to build a complete working virtual prototype directly from a given ESL model, one still has to perform several design steps manually. The work-at-hand tackles this problem by introducing bridge components already in the ESL model. These components influence Design Space Exploration (DSE) by adding their characteristics like cost and latency into evaluation. The complete system is divided into several subsystems connected through bridges, we call this process communication-driven decomposition. Once an optimized implementation solution is found by DSE and selected by the designer, every subsystem of this ESL model is handed over to the individual synthesis tool. Here, if two subsystems will be synthesized by different tools, the bridge connecting these two subsystems will be automatically duplicated into two instances and assigned to each subsystem. Then, synthesis tools generate code for each subsystem (including the bridge inside each subsystem). In the last step, the system integration process merges the corresponding bridge pairs together to build a complete virtual prototype. To automate the proposed design flow, we have developed a framework that automatically divides an ESL model into subsystems and synthesizes the interfaces for all bridges which strongly simplifies system integration. The designer is therefore free from the interface realization. Hence, the overall design development cycle is shortened. As a proof of concept, a distributed control application is presented to give evidence of the proposed technique's applicability and the achieved productivity gain.