Failure Analysis and Reliability of 3D Integrated Systems

The technology of 3D IC integration is highly probable to achieve the demand for high performance, better reliability, miniaturization and lower-priced portable electronic products. Since the through silicon via (TSV) is the heart in 3D IC integration architectures, the reliability issues of TSV interconnects should be extremely concerned. Due to the large thermal expansion mismatch among the Cu, Si, and SiO 2 , the induced thermal stresses and strains can occur and become the driving forces for failures in TSV interconnects. Hence, the stress analyses and failure mode investigation for TSVs are in urgent need. Among the typical failures, the mostly common failure type is delamination, which will be caused when lower energy release rate (ERR) or higher critical stresses at interfaces are presented. In this study, the finite element modeling (FEM) for a symmetrical single in-line copper filled TSV with redistribution layer is illustrated. Two kinds of horizontal cracks that embedded in the interface of SiO 2 passivation and Cu seed layer (Cu pad delamination cases) are introduced to realize the interfacial ERR, where is also the critical stress area that observed from finite element analysis. The significance of design parameters such as crack length, TSV diameter, TSV pitch, depth of TSV, SiO 2 thickness and Cu seed layer thickness are also brought up. The methodology of design of experiments (DoE) has been adopted to capture the most important mechanical parameters of the TSV to comprehend the corresponding ERR. It is believed that these results would be helpful to avoid delamination of TSV interconnects in 3D IC integration.

Over the past two decades, 3D techniques combined with heterogeneous integration, combining different functions and materials, have emerged as a key enabler for overcoming the physical and scaling limits of traditional 2D integration. These approaches are now expanding across multiple domains, including CMOS, memories, photonics, imagers, and RF systems, with the aim of delivering next-generation integrated systems for advanced computing (AI), analog/RF, and imaging applications. In this presentation, we will explore the fundamental techniques, recent advancements, and some challenges associated with achieving integration. Special emphasis will be placed on the role of hybrid bonding and sequential 3D integration schemes, as well as their implications for energy efficiency, device performance, and system-level innovations.3D integration has transitioned from a niche research area to a cornerstone technology in microelectronics, driven by its potential to address high density interconnect and traditional 2D scaling bottlenecks for several applications and enable heterogeneous integration at unprecedented scales. At the heart of this technological evolution are advanced schemes such as wafer thinning, Through-Silicon Vias (TSVs), hybrid bonding, and sequential 3D integration techniques. These techniques have been pivotal in shrinking the interconnect length, reducing latency, and enhancing data bandwidth in computing systems. In parallel, developments in wafer-to-wafer, die-to-wafer, and chiplet integration are enabling the seamless merging of diverse materials enabling functionalities such as logic, memory, photonics, and RF. Compact form factors are achieved enabling to boost performances of the most demanding applications such as Artificial Intelligence or Tb/s transceiver applications [1].Recent studies highlight significant progress in hybrid bonding technology, which achieves high-density interconnects at the submicron scale, thereby optimizing power delivery and thermal management in stacked devices [2]. Meanwhile, sequential 3D integration [3][4] where layers of transistors are fabricated sequentially on the same substrate, is emerging as a game-changing paradigm. It promises ultra-high-density integration with minimal parasitics, creating new opportunities for energy-efficient and high-performance systems. Several applications are foreseen including C-FETS, memories and imagers [5] .Photonic interconnects will enter in next generation 3D IC integration, addressing challenges in data bandwidth, power consumption and signal integrity and enabling photonic interposers for next generation of components for data centers and communication systems [7]. Similarly, RF [8] and analog domains [9] benefit from 3D stacking by improving front-end module integration with specific materials (III-V, HR, ...), leading to enhanced performance and higher frequencies.Despite these achievements, significant challenges remain. Thermal dissipation is a critical bottleneck [10] , particularly in densely 3D stacked architectures where hotspots can severely impact reliability and performance. Moreover, the mechanical stresses induced during bonding and processing can affect device yield and long-term stability. Our recent work in advanced thermal management and stress engineering underscores the need for interdisciplinary approaches to address these challenges. Solutions such as microfluidic cooling, novel materials for thermal interface layers and specific bonding technologies are being actively explored. Furthermore, while heterogeneous integration is currently feasible at the wafer scale—such as wafer-to-wafer hybrid bonding, which is already in mass production—expanding application fields will require advancements in die-to-wafer integration techniques.Looking ahead, the convergence of 3D integration with emerging paradigms such as neuromorphic computing, quantum technologies, multispectral and smart imagers, and advanced packaging promises to redefine system design at all levels. The synergy between 3D technologies and heterogeneous integration of advanced materials, such as 2D semiconductors, III-V, ferroelectric or oxide semiconductor [11] materials, further expands the horizon for innovation.In conclusion, 3D integration has proven to be a transformative force in microelectronics, offering pathways to overcome traditional limitations and unlock new performance dimensions. Intensive researches worldwide continues contribute to push the boundaries of what is possible, paving the way for smarter, more efficient, and highly integrated systems.

3D technology is envisioned to offer advanced integration capabilities, enabling heterogeneous system integration and offering improved performance and reduced power consumption thanks the so-called Through Silicon Vias (TSVs). Nevertheless, 3D integration is facing strong thermal issues due to its higher power density and reduced heat dissipation properties. In previous studies, it has been often reported the use of TSV insertion techniques for thermal mitigation in 3D stacked circuits. However, due to the thin oxide layer isolating TSVs from silicon substrate, the expected thermal mitigation is actually not effective for the current TSV technologies. This paper firstly provides an analytical study to project the potential benefits and drawbacks of using TSVs for thermal mitigation. Detailed FEM simulations and experimental silicon data from a dedicated thermal test chip are then used to confirm the projections and demonstrate that TSVs may even increase the temperature of hotspots. This paper secondly reports the study of the thermal performance of multiple TSV arrays using thermal simulations for various system-level configurations, including a WideIO compatible 3D circuit. Similar results are obtained where, besides not alleviating thermal issues, TSVs may produce exacerbated hotspots. The results presented in this paper indicate that the use of additional area costly TSVs for thermal mitigation is not worthy.

New electronic devices with small size and low power consumption are in demand in recent years. Miniaturization and complex product are required in modern electronics for more functionality in the smaller electronic package. To overcome such issues, 3D packages or package on package (PoP) are introduced. The 3D packaging is stacking of chip on top of another which is emerging as a powerful technology that satisfies such integrated circuit (IC) package demands. A 3D package using through silicon vias (TSVs) has emerged as an effective technology for future interconnection requirements. The mismatch of coefficient of thermal expansion (CTE) of the SiO2 and copper used in TSV can induce a lot of thermal stresses. The stress developed at interfaces results in the interfacial delamination of TSV, which is mainly driven by a shear stress concentration at the point. The developed thermal stresses are critical for the thermo-mechanical reliability of the 3D package. In this paper, the effect of package structure on the failure metric of the 3D package has been studied. J-integral has been used to quantify the crack driving force. The crack is modeled at the TSV and BEOL (Back End of the Line) and the die-substrate thickness is varied and studied during chip attachment process and under thermal cycling load for optimizing the die and substrate thickness design [1]. Finite Element method have been used to analyze the thermo-mechanical stresses and fracture parameters in TSV structures 3D package. For this study, full field compact modeling methodology [2] has been leveraged for the ease of FEA using ANSYS Workbench 17.2. An optimized package assembly was obtained to reduce the crack driving energy at the TSV region and in the BEOL dielectric layer. A design approach has been proposed to mitigate brittle failure issues thus improving the thermo-mechanical reliability of the 3D package.

3D IC technologies are now approaching the innovation and business activities of semiconductor industries. 3D IC can be heterogeneous from different chip, interposer or substrate to integrate into a single package by using through silicon via (TSV) technique. With increasing functionality and performance at minimum cost and power dissipation, wide I/O memory VLSI technologies are being aggressively scaled to meet this demand. Stack memory chips using TSV technique will lead to increase a significant manufacturing challenge for semiconductor industries. TSV formation and interconnected reliability on the intermetallic compound (IMC) between the metal-metal bounded micro-bumps are crucial for 3D IC technologies. As the number and power of IC increases, lots of heat will be generated and, in turn raises the junction temperature. This will greatly deteriorate the performance of IC. Heat dissipation for 3D IC, when the power density exceeds 100W/cm2, is an important design concern before marketing. In this paper, high density TSV formed by an ultrafast pico-second laser to evaluate the behavior between manufacturing process and silicon material is presented. In addition, thermal management using finite element analysis to predict the reliability of TSV model is demonstrated.

The alignment and overlay performance of an ASML PAS5000 waferstepper is reviewed in relation to 3D integration and wafer level packaging (WLP) processes. The alignment system can be used to measure substrate distortions in wafer bonding and waferthinning processes and it can align with high accuracy through thick films. Moreover, it is demonstrated that in through silicon vias (TSV) processing the front- to backwafer overlay accuracy is limited by the etch process, not by the alignment system. An accurate fully functional alignment system can therefore be used to characterize and improve the overlay in 3D integration and WLP processes.

Nowadays, three-dimensional (3D) integration has been widely applied in semiconductor and electronics industry. When 3D integration applied in MEMS (micro electromechanical system) packaging, it is possible to stack host MEMS chip/wafer with other chips/wafers (such as ASIC) to lower package profile and realize area array sensor system. In this paper, a miniaturized piezoresistive pressure sensor system with TSV structure has been designed to demonstrate the application of TSV in MEMS packaging. TSV in pressure sensor chip is designed to provide communication paths for electrical signals. Cu/Sn bump is electroplated after exposing TSV from backside and backside metallurgy. Signal read-out chip contains redistribution circuits and Au studs. The pressure sensor chip and signal read-out chip are flip chip bonded using Au-Sn eutectic bonding. To realize this pressure sensor system, a systematic process flow including piezoresistors fabrication and circuits patterning, TSV process, flip chip bonding, polymer hermetic sealing is designed and implemented experimentally.

3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC integration. They are different and in general the through-silicon via (TSV) separates 3D IC packaging from 3D Si/IC integrations since the latter two use TSV but 3D IC packaging does not. 3D Si integration and 3D IC integration are different. 3D IC integration stacks up the thin chips with TSV and microbump, while 3D Si integration stacks up thin wafers with TSV alone (i.e., bumpless). TSV is the heart of 3D Si/IC integrations and is the focus of this investigation. Also, the state-of-the-art, challenge, and trend of 3D integration will be presented and examined. Furthermore, supply chain readiness for high volume manufacturing (HVM) of TSVs is discussed.

Three-dimensional (3D) integration wherein multiple layers of planar devices are stacked and interconnected using through silicon vias (TSV). This technology offers great potential improvement over the traditional 2D planar integrated circuits by many ways. A key issue in 3D integration is fabricating ultrathin wafer with TSV. This paper presents a method to fabricate ultrathin wafer by a locally selective thinning technique. Deep reactive ion etching (DRIE) has been utilized to thin the wafer and to prepare the high aspect ratio vias, which are filled with copper by using bottom-up electroplating technique. This method simplifies the fabricating process of ultrathin wafer, comparing to the conventional technology, which grinds the whole wafer with temporary supporting substrate. The surface of thinned wafer has been examined by shadow moiré co-planarity measuring system and the result is acceptable for following bonding process. The experimental results verify the feasibility of proposed method.

Void growth in through silicon vias (TSVs) has been imaged by X-ray microscope without physical cross sectioning. In additional, a finite element stress modeling is used to study the stress-assisted void growth. Fabrication of through silicon vias (TSVs) is challenging and often hampered by the presence of seam-line or voids inside the TSVs as pre-existing void. Annealing these TSVs induces large hydrostatic stress gradient distribute around the pre-existing void. This hydrostatic stress gradient is the driving forces for the vacancies to diffuse to the pre-existing void region and causing void growth. Because physical cross sectioning of TSVs is not required for the 8KeV lab-based X-ray microscope, the same TSVs can be imaged before and after annealing. Void growth is observed at the pre-existing void location after annealing in TSVs with 5μm in diameter and 26 μm of depth. Stresses in a copper-filled TSV with a pre-existing void were simulated by finite element methods and will be presented. The maximum of hydrostatic stress gradient is found to be around the void when cool down from annealing temperature to room temperature. The comparison between simulated results and experimental data show that void growth in TSV is stress-assisted, where vacancies diffuse and coalesce at the void as a result of the hydrostatic stress gradient.

This work will specifically detail the development of a processing and fabrication route for a three-dimensional asynchronous field-programmable gate array (3D-AFPGA) design based on an extension of pre-existing two-dimensional-field-programmable gate array (2D-FPGA) tile designs. The periodic nature of FPGAs permits the use of an alternative approach, whereby the design entails splitting the FPGA design along tile borders and inserting through silicon vias (TSVs) at regular spatial intervals. This serves to enable true 3D performance (i.e., full 3D signal routing) while leaving most of the 2D circuit layouts intact. 3D signal buffers are inserted to handle communication between vertical and adjacent neighbors. For this approach, the density of vertical interconnections was shown to be determined by the size of the bond pads used for tier–tier communications and bonding. As a consequence, reducing bond pad dimensions from 25 μm to 15 μm, or 10 μm, bond pads are preferred to increase the connectivity between layers. A 3D-AFPGA mockup test structure was then proposed for completing development and exercising the 3D integration process flows. This mockup test structure consists of a three-tier demonstration vehicle consisting of a chip-to-wafer and a subsequent chip-to-chip bond. Besides, an alternate copper bonding approach using pillars was explored. Although the intended application is for the 3D integration process compatible with the 3D AFPGA design, the test structure was also designed to be generally applicable to various applications for 3D integration. Because of the importance of thermal management of 3D-AFPGA, it is important to predict the temperature distribution and avoid the maximum junction temperature. The numerical thermal modeling for predicting the equivalent thermal conductivity in every layer and the 3D temperature distribution in the 3D-AFPGA are developed and discussed as well.

This study presents a double-layer atom chip that provides users with increased diversity in the design of the wire patterns and flexibility in the design of the magnetic field. It is more convenient for use in atomic physics experiments. A negative photoresist, SU-8, was used as the insulating layer between the upper and bottom copper wires. The electrical measurement results show that the upper and bottom wires with a width of 100 µm can sustain a 6 A current without burnout. Another focus of this study is the double-layer atom chips integrated with the through silicon via (TSV) technique, and anodically bonded to a Pyrex glass cell, which makes it a desired vacuum chamber for atomic physics experiments. Thus, the bonded glass cell not only significantly reduces the overall size of the ultra-high-vacuum (UHV) chamber but also conducts the high current from the backside to the front side of the atom chip via the TSV under UHV (9.5 × 10−10 Torr). The TSVs with a diameter of 70 µm were etched through by the inductively coupled plasma ion etching and filled by the bottom-up copper electroplating method. During the anodic bonding process, the electroplated copper wires and TSVs on atom chips also need to pass the examination of the required bonding temperature of 250 °C, under an applied voltage of 1000 V. Finally, the UHV test of the double-layer atom chips with TSVs at room temperature can be reached at 9.5 × 10−10 Torr, thus satisfying the requirements of atomic physics experiments under an UHV environment.

In this paper we present the process and electrical results of a 3D integration using through silicon vias (TSV). A flash memory chip has been directly connected to a processor die. The TSVs have been applied from the wafer front-side into a fully processed advanced CMOS 300 mm wafers using a via last approach. After dry etching the 20 by 107 μm holes into the substrate an isolation and barrier seed films are deposited and then filled with copper. The electrical connection between the pad level of the processor chips and the interface to the external connections is realized with a two level redistribution wiring. Subsequently the wafer is flipped, temporary bonded to a carrier wafer, thinned and the TSVs are connected from the wafer backside. Finally the flash chips are assembled to the controller die using a die-to-wafer (D2W) technique. Electrical tests have been conducted and a high yield after TSV processing and assembly determined. The isolation properties and electrical resistance was measured. The linear current in stress transistors was used to define a keep out zone.

The most significant challenge for continued integration of complex systems is energy efficiency. 3D heterogeneous stacking of diverse circuit blocks is one of the most promising solutions. The tutorial will focus on three-dimensional integrated circuits (3D ICs) consisting of multiple layers of systems integrated vertically using through silicon vias (TSVs). We will discuss advantages and challenges of current 3D TSV-based technologies and how to exploit various options through tradeoffs and well-educated choices for designing energy efficient heterogeneous systems. Comparisons between various TSV models and layout solutions will be presented and discussed. Influence of TSV-induced thermo-mechanical stress on devices and interconnects will be discussed. Influence and design trade-offs of temperature distribution on system performance and power dissipation will be discussed. As time permits we will also look towards the horizon, exploring monolithic 3D systems, a variety of new materials such as carbon-nanotubes, and the potential of an abundance of energy efficient interconnects.

Three-dimensional (3D) integration has been considered as the most promising method to overcome the interconnection bottleneck with through-silicon vias(TSVs) served as vertical signal channels. Three-dimensional integrated circuits (3D IC) meet the demands of high throughput, high scalability and low power consumption for future generation integrated circuits. Crosstalk is the dominant problem in signal integrity. While TSVs are bundled together as a cluster, the crosstalk coupling noise may lead to transmission errors. In this paper, we study several influencing factors of the crosstalk in the TSVs. Variations of space between two TSVs nets, different rise time of an attacking signal, various TSV stacking layers and three different types of communication models are modeled and analyzed to master their effect on the TSVs crosstalk. In order to verify the influence factors above, this paper proposes an equivalent electrical model of TSVs for crosstalk.