Fair queueing architectures for high-speed networks

Self-Clocked Fair Queueing (SCFQ) algorithm has been considered as an attractive packet scheduling algorithm because of its implementation simplicity, but it has unbounded delay property in some input traffic conditions. In this paper, we propose a Rate Proportional SCFQ (RP-SCFQ) algorithm which is a rate proportional version of SCFQ. If any fair queueing algorithm can be categorized into the rate proportional class and input is constrained by a leaky bucket, its delay is bounded and the same as that of Weighted Fair Queueing (WFQ) which is known as an optimal fair queueing algorithm. RP-SCFQ calculates the timestamps of packets arriving during the transmission of a packet using the current value of system potential updated at every packet departing instant and uses a starting potential when it updates the system potential. By doing so, RP-SCFQ can have the rate proportional property. RP-SCFQ is appropriate for high-speed packet-switched networks since its implementation complexity is low while it guarantees the bounded delay even in the worst-case input traffic conditions.

Deficit round-robin is a packet scheduling algorithm devised to provide fair queueing in the presence of variable length packets (see Shreedhar, M. and Varghese, G., IEEE Trans. on Networking, vol.4, p.375-85, 1996). DRR can be implemented at O(1) complexity provided that each flow is allowed to transmit at least one maximum size packet on each round; however, under this constraint, DRR may exhibit high latency and poor fairness. We first generalize previous results known for DRR, related to its latency and fairness. We then introduce a novel DRR implementation technique, called active lists queue method (Aliquem), which allows the above constraint to be relaxed while preserving O(1) complexity, thus achieving better latency and fairness that are comparable to those of more complex algorithms, such as self-clocked fair queueing.

Long Term Evolution(LTE) 시스템은 멀티미디어 서비스와 같은 다양한 서비스를 이동 사용자에게 제공할 수 있다. 실제로 HSPA+(High Speed Packet Access plus)는 다운링크의 비트 율(bit rate)을 크게 향상 시켰으나, 다양한 멀티미디어 서비스에서 요구하는 서비스 품질을 어떻게 만족시킬 것인가에 대한 연구는 매우 미비한 상태이다. 본 논문에서는 proportional fair(PF) 알고리즘을 기반으로 하여 LTE를 위한 효율적인 패킷 스케쥴링 알고리즘을 제안하였다. 제안된 알고리즘에서는 패킷 스케쥴링을 할 때 패킷의 우선순위를 결정하는 가장 중요한 요소인 트래픽 클래스의 가중치와 순간 사용자 데이터 전송율을 최적화 하였다. 또한 다중 셀(multi-cell) 환경에서 LTE를 통해서 사용자에게 전송되는 멀티미디어 트래픽을 시뮬레이션 함으로써 제안된 알고리즘의 성능이 향상되었음을 보였다. The Long Term Evolution (LTE) system is already able to provide a background of variety services for mobile users with multimedia services such as audio, video, and data. In fact, the High Speed Packet Access plus (HSPA+) solution can greatly enhance bit rates on down-link. However, the supporting for multimedia applications with different QoS (Quality of Service) requirements is not devised yet. Hence, in this paper we propose an effective packet scheduling algorithm based on Proportional Fairness (PF) scheduling algorithms for the LTE. In this proposed packet scheduling scheme, we optimized instantaneous user data rates and the traffic class weight which prioritize user's packets. Finally, we evaluated and showed the performance of the proposed scheduling algorithm through simulations of multimedia traffics being transmitted to users over LTE links in a multi-cell environment.

In this paper, we propose a novel TSMB bus system with multiple bidirectional data transmission and time synchronization capability for IEDs(Intelligent Electronic Devices). Unlike the legacy unidirectional TMDS(Transition Minimized Differential Signaling) used for transfer digital video signals, the proposed bus system employs dual high-speed serial TMDS link for sending trigger signals from the FPGA of main processor module and receiving the sampled data from submodules such as either current or potential transformers. For simultaneous triggering multiple submdoules, we also employ the precision timing protocol processing capability in the main processor, which generates the wall clock pulse per second(PPS) synchronized to GPS. Adopting PLL for the PPS signal, we can provide the reference clock of 98.304MHz for supporting the data rate of 491.52 Mbps over each TMDS link. The data rate can support eight 24 bits ADCs for PTs or CTs in the single link, each of which requires 4800 samplings per second. An implemented TSMB bus system with FPGA consists of a single main processor with clock expander and eight submodules, in which each submodule is connected with the bidirectional TMDS link to the FPGA of main processor module. The jitter of 1 PPS between the two main processor modules was measured to be less than 102nsec at the maximum, and the jitter of the TSMB transmission data line was measured to be less than or equal to 660ps at the TP3 point of the receiving side, confirming that the TMDS specification was satisfied. Finally, the proposed time- synchronized multi-directional bus system can contribute to the improvement of the reliability and performance of the algorithm of the intelligent protection relay system through the optimal transmission of equivalent and simultaneous sampling data without the involvement of the processor.

We describe an efficient fair queuing scheme, leap forward virtual clock, that provides end-to-end delay bounds similar to weighted fair queuing (WFQ), along with throughput fairness. Our scheme can be implemented with a worst-case time O(loglogN) per packet (inclusive of sorting costs), which improves upon all previously known schemes that guarantee delay and throughput fairness similar to WFQ. Interestingly, both the classical virtual clock and the self-clocked fair queuing schemes can be thought of as special cases of our scheme, by setting the leap forward parameter appropriately.

For pt.I see ibid., p.509-18 (1997). The total implementation complexity of cell schedulers which aim at approximating the generalized processor sharing (GPS) policy is the combination of the complexity of their system-potential function and the complexity involved in sorting the timestamps in order to select the cell with minimum timestamp for transmission. Given that several scheduling algorithms which use a system-potential function of O(1) complexity have been introduced (among them, the minimum-delay self-clocked fair queueing (MD-SCFQ) algorithm achieves optimal delay and excellent fairness properties), the major contribution to the total complexity comes from the task of sorting the timestamps every time a cell is transmitted or received, which is common to all GPS-related schedulers. In this paper, we present a technique, called the logarithmic calendar queue (LCQ), that can achieve a dramatic reduction of the implementation complexity of a GPS-related scheduler, at the cost of a very small and controllable degradation of the delay bounds. We then use the LCQ to implement MD-SCFQ with reduced complexity. By applying the general methodology for the delay analysis presented in the first part of this paper (Chiussi et al. 1997), we are able to provide a closed-form expression of the delay bounds as a function of the LCQ design parameters, which can be used to optimize the design. The LCQ is not exclusively related to MD-SCFQ, but can be applied to any GPS-related scheduler to simplify implementation complexity.

Cell-free massive multiple-input multiple-output (CF-mMIMO) has attracted considerable attention due to its potential for delivering high data rates and energy efficiency (EE). In this paper, we investigate the resource allocation of downlink in CF-mMIMO systems. A hierarchical depth deterministic strategy gradient (H-DDPG) framework is proposed to jointly optimize the access point (AP) clustering and power allocation. The framework uses two-layer control networks operating on different timescales to enhance EE of downlinks in CF-mMIMO systems by cooperatively optimizing AP clustering and power allocation. In this framework, the high-level processing of system-level problems, namely AP clustering, enhances the wireless network configuration by utilizing DDPG on the large timescale while meeting the minimum spectral efficiency (SE) constraints for each user. The low layer solves the link-level sub-problem, that is, power allocation, and reduces interference between APs and improves transmission performance by utilizing DDPG on a small timescale while meeting the maximum transmit power constraint of each AP. Two corresponding DDPG agents are trained separately, allowing them to learn from the environment and gradually improve their policies to maximize the system EE. Numerical results validate the effectiveness of the proposed algorithm in term of its convergence speed, SE, and EE.

B-ISDNs are required to support a variety of services such as audio, data, and video, so that the guarantee of quality-of-service (QoS) has become an increasingly important problem. An effective fair scheduling algorithm permits high-speed switches to divide link bandwidth fairly among competing connections. Together with the connection admission control, it can guarantee the QoS of connections. We propose a novel fair scheduling algorithm, called virtual-time-based round robin (VTRR). Our scheme maps the priorities of packets into classes and provides service to the first non-empty class in each round. Also, it uses an estimation method of the virtual time necessary to this service discipline. To find the first non-empty class, the VTRR adopts a priority queueing system of O(loglog c) which decreases the number of instructions which need to be carried out in one packet transmission time segment. These policies help the VTRR implementation in software, which presents flexibility for upgrades. Our analysis has demonstrated that the VTRR provides bounded unfairness and its performance is close to that of weighted fair queuing. Therefore, the VTRR has a good performance as well as simplicity, so that it is suitable for high-speed B-ISDN.

Analyzes the performance of an output-buffered asynchronous transfer mode service multiplexer (ATM-SMX) in the North Carolina Information Highway (NCIH). The ATM-SMX is modeled as a discrete-time finite-buffer single-server queueing system, where two types of traffic represent the inputs of the multiplexer: (1) nonreal-time loss-sensitive traffic; and (2) real-time loss-insensitive traffic. The authors assume that there are N identical type 1 sources each modeled as a Bernoulli process. The authors also assume that there is a single type 2 source modeled as a periodic batch arrival where the batch site follows a general distribution. All the slow-speed inputs of the ATM-SMX are multiplexed onto a single high-speed output link, and the service rate is constant. The authors adopt a scheduling policy which suits the characteristics of these two types of traffic. An exact analysis is developed to obtain the waiting time distributions and cell loss probabilities for both types of traffic.

The primary obstacles to high-speed communication, namely, shot noise from ambient light, high-capacitance photodiodes and multipath dispersion, are reviewed, and ways to counter them are demonstrated for a prototypical infrared system. The discussion is limited to the physical-layer issues involved in the design of a single high-speed optical link. The focus is on the downlink (from base station to portable), which is a more challenging problem technically than the uplink for two reasons. First, the complexity of the portable receiver is much more constrained than that of the base station, due to power consumption and cost restrictions. Second, the downlink data rates are likely to be much higher than the uplink rates, because downlink communication will include downloading large executable files and possibly video services, whereas uplink communication will be used for transferring working files and keyboard commands which tend to be much smaller.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In this paper, we present and experimentally evaluate a real-time 10 Gbps free-space optical (FSO) link under varying atmospheric conditions. In bandwidth-craving wireless technologies due to the ubiquitous consumption by internet of things devices and requiring high data rate online services, unlicensed FSO systems can be a promising candidate to satisfy the network capacity of the existing data communications technologies. In this work, we verify the experiment using small form-factor pluggable transceivers mounted FPGA as a FSO transmitter and receiver. Here, a high-speed single FSO link is proposed and its performance under turbulence and fog conditions using the dedicated indoor atmospheric chamber is evaluated. We show that the proposed system under the turbulence condition with a scintillation index of 0.35 offers the same data rate as the link under a clear channel, while the bit error rate increases from 10−12 to 5 × 10−4.

The demand for faster internet connections to access wireless multimedia applications, Aeronautical Communication Networks (ACNs) and internet services has resulted into rise of developing broadband wireless technologies in recent years. The demand for higher data rates was the backbone for developing wireless communication technologies such as Worldwide Interoperability for Microwave Access (WiMAX), Long Term Evolution (LTE) and High-Speed Packet Access (HSPA). The big challenge with wireless communications lies with providing Quality of Service (QoS) under various environmental challenges and maximizing resource utilization at the same time. In wireless communication, the support for QoS is difficult due to the unpredictable nature of wireless channels. Opportunistic Scheduling plays a big role towards meeting QoS requirements and managing resources in aeronautical communication networks. Various opportunistic schedulers focus on increasing the system capacity of a wireless communication network, while some aim on improving the system’s fairness and throughput. With such interest in opportunistic scheduling, the paper focuses on reviewing recently proposed opportunistic scheduling algorithms, the objectives they were designed for, and their shortcomings. An effective opportunistic scheduling algorithm with hierarchical modulation technique is presented in this paper. The algorithm focuses on the ability to allocate resources between two users with different channel conditions; that is a user with good channel conditions and a user with bad channel conditions, to maximize the system’s throughput and maintain fairness.

UTRAN long term evolution is currently under standardization within 3GPP with the aim of providing a spectral efficiency 2 to 4 times higher than its predecessor HSUPA/HSDPA release 6. Single carrier FDMA has been selected as multiple access for the uplink. This technology requires the subcarriers allocated to a single user to be adjacent. The consequence is a reduced allocation flexibility which makes it challenging to design effective packet scheduling algorithms. This paper provides a search-tree based channel aware packet scheduling algorithm and evaluates its performance in terms of throughput and noise rise distributions. It is shown that, despite measurement errors and high inter-cell interference variability, the proposed algorithm can increase the uplink capacity by 24% for the macro 1 scenario and 19% for the macro 3 scenario.

The research on green cloud computing is indispensable to reduce the emission of carbon as well as to rescue the environment from the hands of global warming, as the climatic change due to the emission of carbon is a critical issue now a days. The green cloud computing mainly concentrates on reducing the amount of cloud resources to condense the emission of carbon. So an effective and efficient scheduling algorithm, Green Task Scheduling (GTS) Algorithm, is proposed in this paper to bring down the amount of cloud resources in use. The proposed algorithm also reduces the hardware cost significantly. As green cloud computing also concentrates to save the energy consumption by providing only the required amount of voltage based on the frequency of work, a technique called as Dynamic Voltage Frequency Scaling (DVFS) is also used in this paper to control the voltage as well as the frequency of the processor without affecting the working performance. The numerical results prove that the makes pan, energy and cost are optimally minimized by implementing GTS along with DVFS in cloud computing environment.

Finding an optimal solution to the problem of scheduling an application modeled by a directed acyclic graph (DAG) onto a distributed system is known to be NP-complete. The complexity of the problem increases when task scheduling is to be done in a heterogeneous computing system, where the processors in the network may not be identical and take different amounts of time to execute the same task. This paper introduces a performance effective task scheduling (PETS) algorithm for network of heterogeneous system, with complexity O(v+e) (p+log v), which provides optimal results for applications represented by DAGs. The performance of the algorithm is illustrated by comparing the schedule length, speedup, efficiency and the scheduling time with existing algorithms such as, heterogeneous earliest finish time (HEFT) and critical-path on a processor (CPOP) and levelized min time (LMT) reported in this paper. The comparison study based on both randomly generated graphs and graphs of some real applications shows that PETS algorithm substantially outperforms existing algorithms