FangTianSim: High-Level Cycle-Accurate Resistive Random-Access Memory-Based Multi-Core Spiking Neural Network Processor Simulator

Herein, a digital–analog hybrid resistive random‐access memory (RRAM) is prepared by integrating the structurally similar SiNx‐based digital‐type RRAM with analog‐type RRAM by heterogeneous integration method. The Pt/SiNx/Ta/Ru is a digital RRAM due to the formation and breakage of the internal silicon dangling bonds conductive filaments, and the TiN/SiNx/Ta/Ru structure is an analog RRAM due to the traps‐filled limit region of the space‐charge limited current. The heterogeneously integrated digital RRAM has good cycling stability and endurance characteristics, and the heterogeneously integrated analog RRAM has high linearity and multistate counting characteristics. This heterogeneous integration approach is useful for the implementation of hybrid digital–analog RRAM.

The analog resistive random access memory (RRAM) is attractive for neuromorphic computing systems as synaptic weights. However, cycling endurance is one of the most important limitations to reliability. In this work, two endurance degradation models for analog RRAM are proposed based on the measurement results. Then, the models are utilized to investigate the impact on in-situ training accuracy. We use the MNIST dataset trained in a 3-layer multilayer perceptron (MLP), with the cycling endurance of RRAM degrading. The results indicate that endurance degradation will decrease the in-situ training accuracy.

Convolutional Neural Networks (CNNs) have achieved excellent performance on various artificial intelligence (AI) applications, while a higher demand on energy efficiency is required for future AI. Resistive Random-Access Memory (RRAM)-based computing system provides a promising solution to energy-efficient neural network training. However, it's difficult to support high-precision CNN in RRAM-based hardware systems. Firstly, multi-bit digital-analog interfaces will take up most energy overhead of the whole system. Secondly, it's difficult to write the RRAM to expected resistance states accurately; only low-precision numbers can be represented. To enable CNN training based on RRAM, we propose a low-bitwidth CNN training method, using low-bitwidth convolution outputs (CO), activations (A), weights (W) and gradients (G) to train CNN models based on RRAM. Furthermore, we design a system to implement the training algorithms. We explore the accuracy under different bitwidth combinations of (A, CO, W, G), and propose a practical tradeoff between accuracy and energy overhead. Our experiments demonstrate that the proposed system perform well on low-bitwidth CNN training tasks. For example, training LeNet-5 with 4-bit convolution outputs, 4-bit weights, 4-bit activations and 4-bit gradients on MNIST can still achieve 97.67% accuracy. Moreover, the proposed system can achieve 23.0X higher energy efficiency than GPU when processing the training task of LeNet-5, and 4.4X higher energy efficiency when processing the training task of ResNet-20.

Power-efficient data processing subsystems performing millions of complex concurrent arithmetic operations per second form part of today’s essential solution required to meet the growing demand of edge computing applications, given the volume of data collected by real-time Internet-Of-Things (IoT) sensors. Adding to it, the in-memory computation designed as memory and processing elements on a single wafer has enabled promising performance improvement in terms of computational power savings by avoiding the memory wall created while accessing the memory array. The Resistive RAM (RRAM), with its simple metal-insulator-metal (MIM) structure, proves to be a very appealing candidate for in-memory computation given its ultralow switching power and its Complementary Metal Oxide Semiconductor (CMOS) process fabrication compatibility. However, despite all advantages, the resistive switching phenomenon in RRAM has an inherent stochastic variability. On the algorithmic side, convolution neural networks (CNN) have gained popularity in image classification applications, and the network’s architecture is memory-intense in nature for memorizing the trained weights. Hence, an RRAM-based CNN system will pave way for a power-efficient image classification system on the edge. Accounting however for the inherent variability in RRAM (inter-device and intra-device), the accuracy of CNN’s prediction is surely expected to drop. This motivates us to quantify the impact of RRAM variability on the CNN trained weights and classification accuracy (prediction loss). In this study, we have constructed a Look-Up-Table (LUT) based model for encoding wide current compliance (2μA to 250μA) 65nm CMOS 1T1R OxRAM’s (TiN/HfO2/Hf/TiN) resistive variability into CNN’s trained weight in a digital regime. The RRAM resistance encoded trained weights are in turn used here to simulate the two extreme CNN architectures, namely, Fully Serial System (FSS) and Fully Parallel System (FPS). The architectures’ prediction variability trends are quantified given its current compliance, RRAM resistive variability, CNN’s convolution matrix sizes (5×5, 3×3, 1×1, and 1×1 max pool), the total number of layers in the CNN as well as the input image pixel size.

This chapter introduces resistive random-access memory (RRAM), a futuristic memory technology that excels its counterparts in terms of reliability, nano-scale dimensions, energy per bit, and fast read/write times. Also, it is promising for use in neuromorphic computing and digital applications. However, the major challenge encountered during the progress of the technology is the presence of leakage current (sneak path current) while using it in crossbar arrays. Various techniques are employed to mitigate the sneak current problem. However, associating a selector with RRAM is an efficient method. To study the one selector-one RRAM (1S-1R) characteristics, the electrical model of the selector, as well as RRAM, is necessary; therefore, this chapter discusses the electrical modeling of selector device (1S), RRAM devices (1R), integration of selector models with the RRAM model (1S-1R), and formation of 1S-1R crossbar arrays. The selector device used to model this is Pt/Ta2O5/TaOx /TiO2/Pt, and the RRAM model adopted is Pt/Ta2O5/TaOx/Pt. Further, various parameters are analyzed, such as R off /R on ratio, nonlinearity, and off-current are improved in the 1S-1R cell compared to RRAM characteristics. Besides, it is perceived that 98% of the sneak path current is mitigated in the 1S-1R crossbar array compared to the 1R crossbar array.

Training Convolutional Neural Networks(CNNs) is both memory-and computation-intensive. The resistive random access memory (ReRAM) has shown its advantage to accelerate such tasks with high energy-efficiency. However, the ReRAM-based pipeline architecture suffers from the low utilization of computing resource, caused by the imbalanced data throughput in different pipeline stages because of the inherent down-sampling effect in CNNs and the inflexible usage of ReRAM cells. In this paper, we propose a novel ReRAM-based bidirectional pipeline architecture, named HUBPA, to accelerate the training with higher utilization of the computing resource. Two stages of the CNN training, forward and backward propagations, are scheduled in HUBPA dynamically to share the computing resource. We design an accessory control scheme for the context switch of these two tasks. We also propose an efficient algorithm to allocate computing resource for each neural network layer. Our experiment results show that, compared with state-of-the-art ReRAM pipeline architecture, HUBPA improves the performance by 1.7X and reduces the energy consumption by 1.5X, based on the current benchmarks.

Analog memory presents a promising solution in the face of the growing demand for energy-efficient artificial intelligence (AI) at the edge. In this study, we demonstrate efficient deep neural network transfer learning utilizing hardware and algorithm co-optimization in an analog resistive random-access memory (ReRAM) array. For the first time, we illustrate that in open-loop deep neural network (DNN) transfer learning for image classification tasks, convergence rates can be accelerated by approximately 3.5 times through the utilization of co-optimized analog ReRAM hardware and the hardware-aware Tiki-Taka v2 (TTv2) algorithm. A simulation based on statistical 14 nm CMOS ReRAM array data provides insights into the performance of transfer learning on larger network workloads, exhibiting notable improvement over conventional training with random initialization. This study shows that analog DNN transfer learning using an optimized ReRAM array can achieve faster convergence with a smaller dataset compared to training from scratch, thus augmenting AI capability at the edge.

Resistive random access memory (ReRAM) has been proven capable to efficiently perform in-situ matrix-vector computations in convolutional neural network (CNN) processing. The computations are often conducted on multi-level cell (MLC) that have limited precision and hence, show significant vulnerability to noises. The binarized neural network (BNN) is a hardware-friendly model that can dramatically reduce the computation and storage overheads. However, XNOR, which is the key operation in BNNs, cannot be directly computed in-situ in ReRAM because of its nonlinear behavior. To enable real in-situ processing of BNNs in ReRAM, we modified the BNN algorithm to enable direct computation of XNOR, POPCOUNT and POOL based on ReRAM cells. We also proposed the complementary resistive cell (CRC) design to efficiently conduct XNOR operations and optimized the pipeline design with decoupled buffer and computation stages. Our results show our scheme, namely, ReBNN, improves the system performance by $$25.36\times$$ and the energy efficiency by $$4.26\times$$ compared to conventional ReRAM based accelerator, and ensures a throughput higher than state-of-the-art BNN accelerators. The correctness of the modified algorithm is also validated.

Convolutional Neural Networks (CNNs) play a vital role in machine learning. CNNs are typically both computing and memory intensive. Emerging resistive random-access memories (RRAMs) and RRAM crossbars have demonstrated great potentials in boosting the performance and energy efficiency of CNNs. Compared with small crossbars, large crossbars show better energy efficiency with less interface overhead. However, conventional workload mapping methods for small crossbars cannot make full use of the computation ability of large crossbars. In this paper, we propose an Overlapped Mapping Method (OMM) and MIxed Size Crossbar based RRAM CNN Accelerator (MISCA) to solve this problem. MISCA with OMM can reduce the energy consumption caused by the interface circuits, and improve the parallelism of computation by leveraging the idle RRAM cells in crossbars. The simulation results show that MISCA with OMM can achieve 2.7× speedup, 30% utilization rate improvement, and 1.2× energy efficiency improvement on average compared with fixed size crossbars based accelerator using the conventional mapping method. In comparison with GPU platform, MISCA with OMM can perform 490.4× higher on average in energy efficiency and 20× higher on average in speedup. Compared with PRIME, an existing RRAM based accelerator, MISCA has 26.4× speedup and 1.65× energy efficiency improvement.

The transition from idealized memristor models to physical implementations, such as resistive random access memory (RRAM) devices, is pivotal for advancing neuromorphic circuits in hardware. However, real‐world RRAM devices face challenges due to inherent variability and fabrication tolerances, which hinder their adoption. This study presents the variability intensity model (VIM), a statistical framework designed to assess variability in RRAM devices. The VIM is employed to evaluate the resilience of a memristor‐based Hindmarsh–Rose circuit, which models neuronal behavior in biological systems. The results indicate that the circuit exhibits heightened sensitivity to variability in high‐conductance states, while demonstrating increased tolerance in low‐conductance states. This observation is consistent with RRAM characteristics, where conductance variability decreases as conductance increases. Furthermore, robust spiking dynamics are observed, though the bursting behavior remains sensitive, leading to critical parameter constraints for RRAM devices. By employing a variability model based on real‐world measurements, this work establishes a crucial foundation for the implementation of memristor‐based Hindmarsh–Rose circuits in hardware, where variability is a paramount consideration.

Improving liquid state machines through iterative refinement of the reservoir

Enhancing high-speed digital systems: MVL circuit design with CNTFET and RRAM

In spiking neural networks (SNN), information is considered to be encoded mainly in the temporal patterns of their firing activity. Temporal integration of information plays a crucial role in a variety of cognitive processes, such as sensory discrimination, decision-making, or interval timing. However, it is rarely considered in traditional computational SNN models. In this paper, we investigate the influence of temporal integration on the computational performance of liquid state machine (LSM) from two aspects: the synaptic decay constant and time delay from presynaptic neurons to the output neurons. LSM is a biologically spiking neural network model for real-time computing on time-varying inputs, where the high dimensionality of dynamical spikes is transformed into smoothly changing states through synaptic integration into the readout neuron. Our experimental results show that increasing the decay constant of synapses from SNN to the output neuron can remarkably improve the computational performance due to the enhancement of temporal integration. Moreover, transmission delays have an even larger impact on the richness of dynamical states, which in turn significantly increase the computational accuracy of SNN. These results may have important implications for the modeling of spiking neural networks with excellent computational performance.

Deep neural networks (DNNs) are tremendously applied in artificial intelligence field. While the performance of DNNs is continuously improved by more complicated and deeper structures, the feasibility of deployment on embedded system remains as a critical problem. Neuromorphic system designs based on resistive random-access memory (ReRAM) provide an opportunity for power-efficient DNN employment. However, it encounters the challenge of limited programming resolution. A quantized training method is proposed in this paper to enhance the performance of neuromorphic systems based on ReRAM. Different from previous methods in which a dedicated regularization term is used in loss function to constrain parameter distribution, our quantized training method deals with training and quantization at the same time to alleviate the impact of limited parameter precision. Models with discrete parameters obtained after training can be directly mapped onto ReRAM devices. We implement experiments on image recognition tasks using multi-layer perceptron (MLP) and convolution neural network (CNN). The results verify that the quantized training method can approximate the accuracy of full-precision training, e.g., a two-layer MLP based on binary ReRAM only decreases the classification accuracy by 0.25% for MNIST dataset. In addition, we carefully investigate and present the importance of layer size under the ReRAM's low programming resolution, the different parameter resolution demands for convolution layer and fully connected layer, and system robustness to ReRAM variations after quantized training. The codes are available at https://github.com/qingyangqing/quantized-rram-net.

Resistive random access memory (ReRAM) demonstrates the great potential of in-memory processing for neural network (NN) acceleration. However, since the convolutional neural network (CNN) is widely known as compute-bound, current ReRAM-based accelerators are not able to support CNN efficiently. In this paper, we for the first time propose the CNN accelerator with Winograd's convolution on ReRAM (CNNWire), which minimizes the multiplications to enable fast and efficient CNN inference. We realize the convolution with Winograd Processing Element (WPE) based on convolutional tiles. Interconnections between WPEs are designed aiming to improve the data reuse. Finally, we introduce the full mapping flow to implement the Winograd convolution The results show that CNMWire gains 3.85x energy efficiency boosting and 3.24x speedup on average among different CNN benchmarks, compared with traditional GEMM based mapping. © 2019 ACM.