Fast algorithms for thermal constrained performance optimization in DAG scheduling on multi-core processors

Multi-core processors have become an integral part of mainstream high performance computer systems. In parallel, exponentially increasing power density and packaging costs have necessitated system level thermal management solutions for multi-core systems. Dynamic thermal management (DTM) techniques monitor on-chip temperature continuously and typically employs dynamic voltage and frequency scaling (DVFS) to lower the temperature when it exceeds a pre-defined threshold. State-of-the-art DTM solutions for multi-core systems include distributed DVFS (where each core can scale the voltage/frequency individually) and global DVFS (where all cores scale voltage/frequency simultaneously). Distributed DVFS generally offers higher performance than global DVFS, but it is hard to implement and has major scalability issues.

In order to improve the solution accuracy of the lightning attachment algorithm in dealing with constrained optimization problem, an improved constrained lightning attachment algorithm is proposed in this paper. Firstly, the parameter setting of the constraint processing technology was improved, and the constraint violation degree of all individuals in the population was added to further distinguish between feasible individuals and infeasible individuals; Secondly, several stages in the lightning attachment procedure optimization algorithm are improved, including the performance enhancement stage, the uplink leader stage, the downlink leader stage and so on. The improved constrained lightning attachment procedure optimization algorithm proposed in this paper is compared with the other three constrained optimization algorithms on the standard test function g01-g13. The results show that the algorithm proposed in this paper has certain advantages in solving precision.

Thermal management becomes a prominent issue in system design for both server systems and embedded systems. A system could fail if the peak temperature exceeds its thermal constraint. This research studies thermal-constrained scheduling for frame-based real-time tasks on a dynamic voltage/speed scaling system. Our objective is to design speed schedulers for real-time tasks by utilizing dynamic voltage/speed scaling to meet both timing and thermal constraints. Two approaches are proposed: One is based on the minimization of the response time under the thermal constraint, and the other is based on the minimization of the temperature under the timing constraint. We present detailed schedulability analysis for both proposed approaches. Our data show that our proposed proactive approaches outperform existing reactive ones.

Processor architectures has taken a turn toward many-core processors, which integrate multiple processing cores on a single chip to increase overall performance, and there are no signs that this trend will stop in the near future. Many-core processors are harder to program than multicore and single-core processors due to the need for writing parallel or concurrent programs with high degrees of parallelism. Moreover, many-cores have to operate in a mode of strong scaling because of memory bandwidth constraints. In strong scaling, increasingly finer-grain parallelism must be extracted in order to keep all processing cores busy.Task dataflow programming models have a high potential to simplify parallel programming because they alleviate the programmer from identifying precisely all intertask dependences when writing programs. Instead, the task dataflow runtime system detects and enforces intertask dependences during execution based on the description of memory accessed by each task. The runtime constructs a task dataflow graph that captures all tasks and their dependences. Tasks are scheduled to execute in parallel, taking into account dependences specified in the task graph.Several papers report important overheads for task dataflow systems, which severely limits the scalability and usability of such systems. In this article, we study efficient schemes to manage task graphs and analyze their scalability. We assume a programming model that supports input, output, and in/out annotations on task arguments, as well as commutative in/out and reductions. We analyze the structure of task graphs and identifyversionsandgenerationsas key concepts for efficient management of task graphs. Then, we present three schemes to manage task graphs building ongraph representations, hypergraphs, andlists. We also consider a fourth edgeless scheme that synchronizes tasks using integers. Analysis using microbenchmarks shows that the graph representation is not always scalable and that the edgeless scheme introduces least overhead in nearly all situations.

As processor power density increases, thermal and power control becomes critical for application processing. In this paper, we consider network applications which feature ON/OFF execution pattern, that causes frequent temperature and power consumption changes in the processor. A novel power aware thermal management algorithm is designed to achieve power saving in multicore processors by employing a vacation scheme. We implement the scheme through the idle states (C-state) provided by the OS in the CPU and show their effectiveness both through analysis and experimental data. Then, we apply our scheme with the thermal constraint and propose a heterogeneous load distribution, which creates more opportunities for power saving. Besides maintaining processor temperature below the temperature constraint, our technique achieves higher sustainable load and better power saving with minimum latency increase compared to existing thermal management techniques. To the best of our knowledge, this is the first work to discuss and develop vacation algorithm considering power, temperature and latency for network application on a general purpose multicore processor.

Task graphs are one of the most used models for representing parallel computations. The structures of these graphs are sometimes obtained when compiling the parallel programs. In many other cases, however, they can be determined only at run time. In this paper, we study the scheduling of parallel computations whose task graphs are generated at run time. We obtain a simple optimal scheduling policy for the stochastic minimization of the running time of task graphs when these graphs are generated according to some specific statistical laws. >

Many of today’s complex Cyber-Physical Systems (CPSs) are represented as a set of independent co-executing real-time control applications, where each such application is represented as a precedence-constrained task graph. The applications execute in infinite loops, periodically acquiring data from the environment through sensors at a particular frequency, processing the same, and then producing processed data via actuators. These CPSs often execute under stringent resource constraints (such as limited energy budgets) in distributed networked environments and may be heterogeneous to be able to satisfactorily meet stipulated performance specifications. This work presents a list-based energy-aware scheduler called DPMRS for a set of real-time control applications co-executing in a heterogeneous distributed environment. DPMRS introduces a novel approach for the integrated behavioural representation of a set of co-executing real-time DAG-structured applications. Each task in this integrated representation is then scheduled by determining its relative execution start time on a particular processor, which operates at an appropriately chosen frequency when the task runs on this processor. The overall objective of DPMRS is to minimize aggregate energy consumed in the execution of all tasks. The efficacy of the proposed scheduler has been exhibited through extensive simulation experiments using benchmark task graphs from different application domains. Additionally, a case study on automotive control systems has been included to show the applicability of the proposed work in real world settings.

Duplication-based scheduling techniques are more appropriate for fine grain task graphs and for networks with high communication latencies. However, most of the algorithms are developed under the assumption of fully connected processor network and with prohibitively high O(v4) time complexity. An insertion based duplication algorithm is proposed for precedence constrained task graphs, for working with limited interconnection constrained processors. It duplicates only the most important immediate parents of a task, that too if critical. Results are presented for benchmark random task graphs, having widely varying shape and cost parameters for the clique, Hypercube and an extensible and fault tolerant binary de Bruijn (undirected) multiprocessor network. The average performance degradation, due to interconnection constraints, is about 21% in comparison to fully connected processor network. Further, the schedules generated on the fixed degree binary de-Bruijn network are within 5% of the schedules on Hypercube network, whose degree keeps on increasing with size.

Scheduling task graphs under hard (end-to-end) timing constraints is an extensively studied NP-hard problem of critical importance for predictable software mapping on Multiprocessor System-on-chip (MPSoC) platforms. In this work we focus on an off-line (design-time) version of this problem, where the target task graph is known before execution time. We address the issue of scheduling robustness, i.e. providing hard guarantees that the schedule will meet the end-to-end deadline in presence of bounded variations of task execution times expressed as min-max intervals known at design time. We present a robust scheduling algorithm that proactively inserts sequencing constraints when they are needed to ensure that execution will have no inserted idle times and will meet the deadline for any possible combination of task execution times within the specified intervals. The algorithm is complete, i.e. it will return a feasible graph augmentation if one exists. Moreover, we provide an optimization version of the algorithm that can compute the shortest deadline that can be met in a robust way.

To address the serious decline in charge and discharge performance of lithium batteries in low temperatures, this paper proposes a thermal management scheme with pulsating heat pipes, which effectively achieves the advantages of pulsating heat transfer in heat pipes and large-scale equalization heating in aluminum plates. Optimal energy consumption thermal management strategies (OECTMS) and optimal performance thermal management strategies (OPTMS) were proposed. The OECTMS aims to reduce the system energy consumption while ensuring thermal management performance, whereas the OPTMS is intended to maximize the performance of the heating system, ensuring that lithium batteries achieve optimal thermal and electrical performance. Experimental results show that in low-temperature discharge scenarios (−10 °C, −20 °C, and −30 °C), compared with batteries without TMS, the OECTMS implements intermittent heating for the battery, achieving discharge capacities as high as 60.06 Ah, 54.76 Ah, and 48.66 Ah, which correspond to increases of 10.67%, 14.11%, and 29.83%, respectively. For the OPTMS, which applies continuous heating to the battery, the discharge capacities are increased by 19.5%, 23.7%, and 56.6% compared with batteries without TMS at a 0.5C rate. Notably, the battery with the OPTMS, which originally could not discharge at all under −30 °C, achieves a discharge capacity of 61.55 Ah, exhibiting a higher discharge capacity at a 1.5C rate. Furthermore, compared with the OECTMS, the battery temperature under the OPTMS is consistently maintained above 0 °C, and the temperature changes stably throughout the discharge process without temperature spikes. This manuscript introduces pulsating heat pipe technology and proposes a novel low-temperature thermal management scheme and provides new insights for the efficient operation of lithium batteries in low-temperature environments.

The CPU-graphic processing unit (GPU) co-execution of computation kernels on heterogeneous multiprocessor system-on-chip can significantly boost performance compared to the execution on either the CPU or the GPU alone. However, engaging multiple on-chip compute elements concurrently at the highest frequency may not provide the optimal performance in a mobile system with stringent thermal constraints. The system may repeatedly exceed the temperature threshold necessitating frequency throttling and hence performance degradation. We present OPTiC, an analytical framework that given a computation kernel can automatically select the partitioning point and the operating frequencies for optimal CPU–GPU co-execution under thermal constraints. OPTiC estimates, through modeling, CPU and GPU power, performance at different frequency points as well as the performance impact of thermal throttling and memory contention. Experimental evaluation on a commercial mobile platform shows that OPTiC achieves an average 13.68% performance improvement over existing schemes that enable co-execution without thermal considerations.

Pattern matching has been one of the major operations in modern bioengineering especially in Bioinformatics. Prior work on this area have focus on either pursuing mathematically efficient matching algorithms or hardwired approach. As multicore processor are becoming mainstream, developers need to determine how to take advantage of multicore technology for pattern matching. In this paper, we propose a methodology to evaluate pattern search algorithms for DNA on Multiprocessor. Our evaluation methodology is an automatic simulation framework. Starting from a uniprocessor profiling, the framework constructs task graphs for string matching algorithms. Then task graphs are mapped onto multiprocessor. The system's performance is determined by the analytical performance model. With this framework, we can evaluate the performance of different algorithms on multiprocessor. Our case studies show that finite automaton based (Aho-Corasick) is more efficient than shift table based algorithms (SFKSearch and Wu-Manber) on uniprocessor, however, Wu-Manber is 3 times efficient than Aho-Corasick on multiprocessor due to its inherent parallelism.

In this paper, we investigate Dynamic Thermal Management (DTM) policies under soft thermal constraint that allows the thermal constraint to be violated for a user specified period. For single core processor, we develop analytical expression for the optimal frequency policy under the soft constraint such that maximal performance can be extracted. We extend this problem to multi-core processor and provide optimal frequency policy when all cores run at same frequency. We also present LP based approximated formulation that generates frequency policies where each core has separate frequency control and considers leakage power. We use frequency legalization to approximate the frequency into discrete values. Experimental results indicate that 10 degree celsius increase in core temperature for 100sec results in 13% performance gain for single core processor, and 30% performance gain for two-core processor. Without Tmax constraint, the performance improves almost 100% for two-core processor.

Ant colony optimization is an evolutionary approach where a number of ants search for good solutions. Ant Algorithms often show good optimization results. This paper, discusses number of algorithms built using modified ant colony algorithm which are used to solve the problem of assigning each task in a given task graph to a processor in a reconfigurable multi processor architecture so as to minimize the total overall execution time of the tasks. Each group of ants is working collectively to find the interconnection architecture best suited for the task graph and the best scheduling of that task graph on the chosen interconnection architecture. The total execution time is computed according to the knowledge of individual run times of tasks and the communication requirements among tasks. The inter task communication time is dependent on the interconnection processor architecture. The results of using modified ant colony algorithm in reconfigurable parallel processor system are compared with that of using genetic algorithm for solving the same problem.

Dask is a distributed task framework which is commonly used by data scientists to parallelize Python code on computing clusters with little programming effort. It uses a sophisticated work-stealing scheduler which has been hand-tuned to execute task graphs as efficiently as possible. But is scheduler optimization a worthwhile effort for Dask? Our paper shows on many real world task graphs that even a completely random scheduler is surprisingly competitive with its built-in scheduler and that the main bottleneck of Dask lies in its runtime overhead. We develop a drop-in replacement for the Dask central server written in Rust which is backwards compatible with existing Dask programs. Thanks to its efficient runtime, our server implementation is able to scale up to larger clusters than Dask and consistently outperforms it on a variety of task graphs, despite the fact that it uses a simpler scheduling algorithm.