Fast parallel simulation of a manycore architecture with a flit-level on-chip network model

Architectural simulation is time-consuming, and the trend towards hundreds of cores is making sequential simulation even slower. Existing parallel simulation techniques either scale poorly due to excessive synchronization, or sacrifice accuracy by allowing event reordering and using simplistic contention models. As a result, most researchers use sequential simulators and model small-scale systems with 16-32 cores. With 100-core chips already available, developing simulators that scale to thousands of cores is crucial. We present three novel techniques that, together, make thousand-core simulation practical. First, we speed up detailed core models (including OOO cores) with instruction-driven timing models that leverage dynamic binary translation. Second, we introduce bound-weave, a two-phase parallelization technique that scales parallel simulation on multicore hosts efficiently with minimal loss of accuracy. Third, we implement lightweight user-level virtualization to support complex workloads, including multiprogrammed, client-server, and managed-runtime applications, without the need for full-system simulation, sidestepping the lack of scalable OSs and ISAs that support thousands of cores. We use these techniques to build zsim, a fast, scalable, and accurate simulator. On a 16-core host, zsim models a 1024-core chip at speeds of up to 1,500 MIPS using simple cores and up to 300 MIPS using detailed OOO cores, 2-3 orders of magnitude faster than existing parallel simulators. Simulator performance scales well with both the number of modeled cores and the number of host cores. We validate zsim against a real Westmere system on a wide variety of workloads, and find performance and microarchitectural events to be within a narrow range of the real system.

The multicore revolution and the ever-increasing complexity of computing systems is dramatically changing sys-tem design, analysis and programming of computing platforms. Future architectures will feature hundreds to thousands of simple processors and on-chip memories connected through a network-on-chip. Architectural simulators will remain primary tools for design space exploration, software development and performance evaluation of these massively parallel architectures. However, architectural simulation performance is a serious concern, as virtual platforms and simulation technology are not able to tackle the complexity of thousands of core future scenarios. The main contribution of this paper is the development of a new simulation approach and technology for many core processors which exploit the enormous parallel processing capability of low-cost and widely available General Purpose Graphic Processing Units (GPGPU). The simulation of many-core architectures exhibits indeed a high level of parallelism and is inherently parallelizable, but GPGPU acceleration of architectural simulation requires an in-depth revision of the data structures and functional partitioning traditionally used in parallel simulation. We demonstrate our GPGPU simulator on a target architecture composed by several cores (i.e. ARM ISA based), with instruction and data caches, connected through a Network-on-Chip (NoC). Our experiments confirm the feasibility of our approach.

Fine-Grained Parallel and Distributed Spatial Stochastic Simulation of Biological Reactions

Performance simulation of software for Multiprocessor System-on-a-Chips (MPSoC) suffers from poor tool support. Cycle accurate simulation at Instruction Set Simulation level is too slow and inefficient for any design of realistic size. Behavioral simulation, though useful for functional analysis at high level, does not provide any performance information that is crucial for design and analysis of MPSoC implementations. As a consequence, designers are often reduced to manually annotate performance information onto behavioral models, which contributes further to inefficiency and inaccuracy. In this paper, we use structural performance models to provide fast and accurate simulation of software for MPSoC. We generate structural models automatically using GCC with accurate performance annotation while considering optimizations for instruction selection, branch prediction, and pipeline interlock. Our structural models are able to simulate at several orders of magnitude faster than ISS and provide less than 1% error on performance estimation. These models allow realistic MPSoC design space explorations based on performance characteristics with simulation speed comparable to behavioral simulation. We validate our simulation models with several benchmarks and demonstrate our approach with a design case study of an MPEG-2 decoder.

Typical, numerical structural optimization is well established in improving structural design in its final design phase. The overall product topology is then already defined and structural optimization is “only” used to improve shape and size parameters, which have no influence on the global mechanical topology. Significant decisions have been made already in earlier development stages. However, it is desirable to expand this optimization capabilities to CAE based support for the definition and preliminary design of the general layout, geometrical and structural architecture, equipment configuration and functional requirements. For satellites such a support can be defined as follows: Finding the conceptual geometrical architecture of a satellite satisfying the basic geometrical, mechanical and thermal requirements within an automated optimization process. This includes mainly the (a) topology and geometry of the basic structural components, (b) placements of basic components and equipment and (c) preliminary concept evaluation (e.g. FEM, etc.) Intentionally, the satellite design engineering team should be supplied with a set of feasible or nearly feasible satellite configurations (satisfying the main geometric, mechanical and thermal requirements) serving as a good starting basis for satellite configuration development in early design phases. The design engineers investigate these preliminary conceptual satellite designs for the remaining, typically more specific and more locally acting requirements (e.g. fastening, piping, etc...). In this way the main basic effects guiding satellite design can be taken into account at the very early development stages and, moreover, can be compared with alternative designs to find the best tradeoff. This is a great advantage and progress compared to the traditional design process. Optimization now starts to enter the early and important design phases, the real significant design decisions can now be made by support of optimization techniques. It should be further noted, that our system is not proposed to substitute the design engineers, but to supplement and to enlarge the potentials of the design branch to reach a better design in a shorter time conforming to concurrent engineering issues. In this paper our approach for an automated satellite conceptual design method will be presented, and emphasis is put on demonstration and verification by the satellite GammaBus 1 (the carrier of the Galileo system) as well as other real space applications. Further some main aspects regarding discrete-continuous optimization for structural configuration tasks from an algorithmic point of view are discussed to round out this paper

This paper proposes a parallel cycle-accurate microarchitectural simulator which efficiently executes its workload by splitting the simulation process along time-axis into many intervals. This time-division parallelization is similar to the concept of trace-splitting parallelization but is completely different from this conventional technique because our simulator assures that its result is perfectly equivalent to what a sequential simulator produces. The assurance of the perfect accuracy is endued by a simple failure recovery mechanism; if i-th interval is simulated by a node with an approximate initial machine state which causes invalid result, the interval is simulated again by the node responsible to (i - 1)-th interval and thus having the correct state at the beginning of i-th interval. In order to reduce the possibility of the interval failure for efficiency, the fully cycle-accurate simulation for an interval is preceded by a partial and thus fast micro architectural simulation including that for caches, branch predictors and their interaction in speculative execution. Another important technique is to check the validity of an interval simulation by comparing approximate and correct initial states with respect to their effect to the subsequent execution, rather than the raw values of them. The effectiveness of these techniques are exhibited by our SimpleScalar-based implementation and its evaluation with SPEC CPU95 benchmarks which results that 8-node and 16-node parallel simulations achieve up to 5.8-fold and 9.4-fold speedup respectively

This study proposes an algorithm-aided design (AAD) framework for using daylight in the early phases of architectural design. Within the scope of the proposed AAD, a performance-based design approach has been adopted that can suggest design solutions by optimising with the Genetic Algorithm (GA) that evaluates the results obtained from daylight calculation. The AAD framework was developed using the visual programming application (Dynamo), which interoperates with BIM Software Autodesk Revit. A case study is simulated to show how the algorithm is used to generate, evaluate and evolve a massing study, demonstrating the potential use and implementation of the framework. The investigations focus on the development of the use of daylight in architecture using the advantages of computational design tools.

ADHD and misophonia are developmental neurological disorders that are currently increasing in prevalence due to excessive acoustic and visual pollution. ADHD, which is characterized by a lack of attention and excessive impulsive hyperactivity, and misophonia, which is hypersensitivity to sounds accompanied by a severe emotional and psychological reaction, are both affected by the user’s spatial environment to a great extent. Spatial design can contribute to increasing or decreasing these unfavorable sensory triggers that affect individuals with ADHD and/or Misophonia. However, the role of architectural spatial design as a therapeutic approach to alleviate the symptoms of Misophonia and ADHD has never been proposed before in the literature, despite its accumulative and chronic effects on the user’s experience in everyday life in terms of well-being and productivity. Therefore, the current work discusses this problem of neglecting the potential effect of architectural spatial design on alleviating Misophonia and ADHD. Thus, the objective of the current work is to propose customized architectural spatial design as a therapeutic approach to alleviate Misophonia and ADHD through adopting the compatible architectural trends of minimal and metaphysical architecture. The methodology of the current work includes a theoretical proposal of this customized architectural spatial design for alleviating these two special neurological conditions. This includes introducing and analyzing these two neurological conditions and their relation to and interaction with architectural spatial design, analyzing minimal and metaphysical architectural trends employed in the proposed therapeutic architectural design, and then proposing augmented and virtual reality as auxiliary add-ons to the architectural spatial design to boost its therapeutic effect. Minimal architecture achieves the “no emotion” criteria through reduced forms, patterns, and colors and adopts simple geometry and natural materials to reduce sensory stressors or stimuli, in order to alleviate the loss of attention and distraction prevalent in those with ADHD, as well as allowing the employment of acoustic materials to achieve acoustic comfort and noise blockage for Misophonia relief. Metaphysical architecture leads the hierarchy of sensory experience through the symbolistic, dynamic, and enigmatic composition of forms and colors, which enhance the spatial analysis and cognitive capacities of the inhabitants. Meanwhile, the use of customized virtual and augmented reality environments is an effective add-on to minimal and metaphysical architectural spaces thanks to its proven therapeutic effect in alleviating various neurological disorders and injuries. At this level of intervention, VR/AR can be used as an add-on to minimal-architecture design, to simulate varied scenarios, as minimal design offers a clean canvas for simulating these varied virtual environments. The other option is to build these customized VR/AR scenarios around a specific architectural element as an add-on metaphysical architecture design to lead the sensory experience and enable the user to detach from the physical constraints of the space. AI-generated designs were used as a proof of concept for the proposed customized architectural spatial design following minimal and metaphysical architecture, as well as to provide AR and VR scenarios as add-on architecture to enhance the therapeutic effect of these architectural spaces for Misophonia and ADHD patients. Furthermore, the validity of VR/AR as a therapeutic approach, alongside the customized architectural design, was discussed, and it was concluded that this study proves the need for extended clinical studies on its efficiency in the long run, which will be conducted in the future.

In modern embedded systems, the Hardware-dependent Software (HdS) plays a critical role due to its increasing complexity and development cost. To support HdS development starting in an initial system design phase, fast and accurate preemptive processor models should be provided for simulating the software using register level interface on the host machine environment. This paper presents a strategy for target processor modeling that enables HdS development using native tools running in the host machine. Our approach supports the specification of platform components such as bus data and interruption interfaces and platform specification features, which provides a fast and accurate modeling mechanism. A technique for instruction count estimates is being proposed, which is very accurate and supports the development of driver code plus interruption service routines at a very early design phase. Results demonstrate that a virtual platform specified using the proposed approach can perform fast and accurate software simulation running on host machine, without the need of ISS processor models. The experiments performed validate the proposed approach by showing its efficiency with about three orders of magnitude simulation speed up, including the Dhrystone benchmark in order to assess performance evaluation estimation.

In order to carry out a comprehensive design description of the specific architectural model of AI, the auxiliary model of AI and architectural spatial intelligence is deeply integrated, and flexible design is carried out according to the actual situation. AI assists in the generation of architectural intention and architectural form, mainly supporting academic and working theoretical models, promoting technological innovation, and thus improving the design efficiency of the architectural design industry. AI-aided architectural design enables every designer to achieve design freedom. At the same time, with the help of AI, architectural design can complete the corresponding work faster and more efficiently. With the help of AI technology, through the adjustment and optimization of keywords, AI automatically generates a batch of architectural space design schemes. Against this background, the auxiliary model of architectural space design is established through the literature research of the AI model, the architectural space intelligent auxiliary model, and the semantic network and the internal structure analysis of architectural space. Secondly, to ensure compliance with the three-dimensional characteristics of the architectural space from the data source, based on the analysis of the overall function and structure of space design, the intelligent design of the architectural space auxiliary by Deep Learning is carried out. Finally, it takes the 3D model selected in the UrbanScene3D data set as the research object, and the auxiliary performance of AI’s architectural space intelligent model is tested. The research results show that with the increasing number of network nodes, the model fitting degree on the test data set and training data set is decreasing. The fitting curve of the comprehensive model shows that the intelligent design scheme of architectural space based on AI is superior to the traditional architectural design scheme. As the number of nodes in the network connection layer increases, the intelligent score of space temperature and humidity will continue to rise. The model can achieve the optimal intelligent auxiliary effect of architectural space. The research has practical application value for promoting the intelligent and digital transformation of architectural space design.

Parallel traffic simulation is an application of parallel computing techniques that aims to decrease the computation time by engaging different processors of a multiprocessor system or different computers of a network. Very few traffic simulation models have this capability of parallel simulation. However, it is possible to upgrade a simulation program that is not capable of running parallel simulation by applying the method proposed in this article. The method involves dividing the network into regions and simulating each region under a separate instance of the program. Suitable interprocess communication techniques are employed to exchange data between different regions and synchronize time among the different regions. A significant increase in simulation speed is seen when the proposed method is applied to Paramics, a microscopic time-stepping simulation program.

Emerging massively parallel architectures such as a general-purpose processor plus many-core programmable accelerators are creating an increasing demand for novel methods to perform their architectural simulation. Most state-of-the-art simulation technologies are exceedingly slow and the need to model full system many-core architectures adds further to the complexity issues. This paper presents a fast, scalable and parallel simulator, which uses a novel methodology to accelerate the simulation of a many-core coprocessor using GPU platforms. The main idea is to use. The target architecture of the associated . Simulation of many target nodes is mapped to the many hardware-threads available on highly parallel GPU platforms. This paper presents a novel methodology to accelerate the simulation of many-core coprocessors using GPU platforms. We demonstrate the challenges, feasibility and benefits of our idea to use heterogeneous system (CPU and GPU) to simulate future architecture of many-core heterogeneous platforms. The target architecture selected to evaluate our methodology consists of an ARM general purpose CPU coupled withmany-core coprocessor with thousands of simple in-order cores connected in a tile network. This work presents optimization techniques used to parallelize the simulation specifically for acceleration on GPUs. We partition the full system simulation between CPU and GPU, where the target general purpose CPU is simulated on the host CPU, whereas the many-core coprocessor is simulated on the NVIDIA Tesla 2070 GPU platform. Our experiments show performance of up to 50 MIPS when simulating the entire heterogeneous chip, and high scalability with increasing cores on coprocessor.

Increasing demand for complex and high-performance Analog and Mixed-Signal (AMS) designs has created a significant need for efficient verification methodologies. As modern IC designs integrate more functionality, the time and resources required for verification continue to escalate. Ensuring accurate functionality at different abstraction levels is crucial in system design. In addition, simulation tools often involve a trade-off between simulation speed and accuracy. This trade-off is too extreme for analog simulation especially, due to non-linear behaviour and the possibility of wide range of values at each node, making these simulations time-consuming. A black-box model leveraging polynomial regression technique has been proposed to address this issue. Charge Pump and Ring Oscillator circuits are selected for the verification of the proposed technique. Although analog simulator takes significant overhead in simulation time, Spectre has been used for benchmarking the circuits due to its high accuracy. The black-box model proposed is developed using the data collected from Spectre with a focus on output parameters without considering the intermediate nodes. The regression technique relates the input and the output parameters using a multi-degree polynomial to obtain average output values. This is implemented in SystemVerilog using Real Number Modeling (RNM). Then the average output values are assigned to EEnet (U ser Defined N ettype) by behavioral modeling. This novel curve fitting polynomial approach reduces the prolonged simulation time thereby meeting the Time-to-Market requirements.

The continuous improvements offered by the silicon technology enables the integration of always increasing number of cores on a single chip. Following this trend, it is expected to approach microprocessor architectures composed of thousands of cores (i.e., kilo-core architectures) in the next future. To cope with the increasing demand for high performance systems, many-core designs rely on integrated network-on-chips to deliver the correct bandwidth and latency for the inter-core communications. In this context, simulation tools represent a crucial factor for designing architectures at such scale of integration. The efficient simulation of the interconnection network along with the overall architecture (i.e., cores, cache memories, accelerators, etc.) still represents a complete open issue. This paper proposes a framework based on the COTSon simulator, able of scaling towards heterogeneous kilo-core architectures. Compared with current state-of-the-art architectural simulators, our framework provides not only a full-system architectural simulator, but a full-integrated accurate network-on-chip simulator. The framework shows a well balanced trade-off between simulation speed and accuracy, supporting the power consumption estimation. Experimental results demonstrate the ability of our framework to correctly simulate a large many-core machine and its interconnection network, considering different traffic patterns.

Manycore architectures are mainly composed of a very large amount of computing nodes interconnected with a multiplicity of links usually forming a NoC-like mesh architecture. High-speed links permit to obtain a higher throughput but are much more expensive than normal links, making the interconnection of the system a cost/performance trade-off. Simulating such architectures is very important in order to characterise the optimal network topology for a given problem. In this work we introduce SCALPsim: a simulation framework permitting to evaluate routing algorithms and network properties in 1-D, 2-D and 3-D regular mesh topologies simultaneously using links of different characteristics in terms of latency and throughput. These features are particularly interesting in large scale systems with processing elements grouped into clusters, where communication properties differ largely inside and between clusters. This paper presents the framework and an application based on Cellular Self-Organizing Maps - CSOM.