Fast volatile response in GST/Si waveguides for all-optical modulation

Junction temperature is a critical indicator for health condition monitoring of power devices. Concerning the reliability of emerging silicon carbide (SiC) power semiconductors due to immaturity of new material and packaging, junction temperature measurement becomes more significant and challenging, since SiC devices have low on-state resistance, fast switching speed, and high susceptibility to noise and parasitics in circuit implementations. This paper aims at developing a practical and cost-effective approach for online junction temperature monitoring of SiC devices using turn-off delay time as the thermo-sensitive electrical parameter (TSEP). The sensitivity is analyzed for fast switching SiC devices. A gate impedance regulation assist circuit is designed to improve the sensitivity by a factor of 60 and approach hundreds of ps/°C in the case study with little penalty of the power conversion performance. Also, an online monitoring system based on three gate assist circuits is developed to monitor the turn-off delay time in real time with the resolution within hundreds of ps. In the end, the micro-controller is capable of “reading” junction temperature during the converter operation with less than 0.5 °C measurement error. Two testing platforms for calibration and online junction temperature monitoring are constructed, and experimental results demonstrate the feasibility and accuracy of the proposed approach. Furthermore, the proposed gate assist circuits for sensitivity improvement and high resolution turn-off delay time measurement are transistor based and suitable for chip level integration.

We propose a method for fast bistable switching of chiral-nematic liquid crystals. Fast switching from the focal conic to the planar state can be achieved by applying an in-plane electric field for a short period of time. The in-plane field induces a transient state, which relaxes rapidly to the initial planar state. We demonstrate that the switching time from the focal conic to the planar state could be reduced from 150 to 5 ms by applying an in-plane field instead of a vertical field. We achieved a total response time of less than 10 ms. The proposed device is applicable to a reflective display and to other optical switching devices requiring both fast response time and low power consumption.

To test the hypothesis that the initial O2 uptake kinetics during exercise where the rise in blood flow (and, by implication, O2 delivery) to the working muscles during an abrupt increase in exercise intensity is reduced (i.e., arm exercise performed above the level of the heart) would be faster when preceded by a bout of high-intensity exercise. Eleven physically active males completed two protocols, each consisting of two consecutive bouts of 6 min of high-intensity arm crank exercise separated by 6 min of recovery. In one protocol, the arm crank exercise was performed with the arms below the level of the heart (<HL); in the other, the arms were above the level of the heart (>HL). In the <HL protocol, the VO2 fast component time constant was not significantly affected by prior exercise (35.9+/-8.7 and 35.5+/-8.9 s in bouts 1 and 2, respectively). The amplitudes of the VO2 fast and slow component were respectively significantly higher and significantly lower in the second bout. In the >HL protocol, the amplitudes of the VO2 fast and slow component were unaffected by prior exercise, whereas the VO2 fast component time constant was significantly reduced in the second bout (49.8+/-22.1 vs 40.7+/-13.2 s; P<0.05). The results of this study demonstrate that prior high-intensity exercise caused a significant speeding of the VO2 fast component response during subsequent high-intensity arm crank exercise performed above, and not below, the level of the heart.

In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage ( ${V}_{\textsf {BR}}$ ). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time ( ${T}_{ \mathrm{\scriptscriptstyle ON}}$ ) and turn-off time ( ${T}_{ \mathrm{\scriptscriptstyle OFF}}$ ) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss ( ${E}_{\mathbf {SW}}$ ).

Reconfigurable photonic integrated circuits (PICs) are key elements for emerging applications like photonic sensing, LiDAR, and quantum computing. In such applications, optical switches with fast response and robust fabrication methods are crucial for reprogramming linear optical transformations on demand. Here, we demonstrate a fast thermo-optic switching mechanism on the silicon nitride on insulator platform, leveraging parity-time symmetry breaking. The cladding-free design operating at 775 nm enables optical propagation in a partially metal-covered waveguide with minimal loss-an uncommon phenomenon given the typical absorption associated with metal proximity. The fabricated device exhibits a 7.1 µs rise time for a π phase shift, despite the weak thermo-optic coefficient in silicon nitride. Our design provides reproducible fabrication metrics and holds promises for large-scale photonic networks operating at visible wavelengths.

A multithreaded processor architecture enables fast context switching for tolerating memory access latency and bridging synchronization gap, and thus enables efficient utilization of execution pipelines. However, it cannot prevent all pipeline stalls; stalls will still occur when all processor built-in threads are in a wait state or there are not enough threads in a task to fill up all available context slots, since the mechanism for switching active threads is effective only for processor built-in contexts. In this paper, we propose an architecture that increases the virtual number of built-in contexts and enables seamless task switching by allocating and swapping task contexts hierarchically between processor and memory in a multitasking environment. At the same time, we aim at supporting real-time applications through hierarchical task allocation based on task priority and fast response mechanisms for interrupt requests exploiting the multiple-context architecture. Moreover, we propose two reconfigurable cache applications, a priority-based partitioning cache and a FIFO buffer, and their implementation methods. We have extended the general-purpose RISC processor architecture and are developing a new RISC core which can be used to implement the seamless task switching, fast response to interrupt requests, and the reconfigurable caches, for supporting real-time processing in a multi-tasking environment. we describe the design of the RISC core in this paper.

Motivation: To push high-performance head gradients at 7T for two extreme ends of the spatiotemporal spectrum, namely ultra-fast and ultra-high-resolution whole-brain imaging. Goal(s): To explore exceptionally fast gradient switching times and amplitudes for most efficient imaging using highly-accelerated segmented 3D-EPI. Approach: Whole-brain time series with frame rates up to 90ms per volume (3mm isotropic resolution) and anatomical T2*-weighted images with 350 microns isotropic voxels (within 3.5 minutes) were acquired and used for venography, SWI and quantitative imaging. Results: 1.) Fast and tSNR-efficient time series acquisitions and 2.) ultra-high-resolution whole-brain anatomical images and quantitative maps are demonstrated. Impact: Utilizing highly-accelerated segmented 3D-EPI with high-performance head gradients at 7T, ultra-fast whole-brain fMRI protocols (up to 90ms per volume at 3mm isotropic) and ultra-high-resolution whole-brain anatomical/quantitative imaging with negligible motion blur (350 microns isotropic within 3.5 minutes) become possible.

The introduction of metamaterials into electrochromic (EC) displays has recently inspired a great breakthrough in the EC field, as this can offer a variety of new attractive features, from a very wide gamut of colors to very fast switching times. However, such metamaterial-based EC displays still face significant constraints when developing from single electrodes to full devices, because other supportivecomponents in devices, such as counter electrodes and electrolytes, significantly affect light propagation and the subsequent perceived color quality in metamaterial-based EC devices. Herein, a new, cost-effective device design structured around a new type of porous metamaterial is reported to circumvent the critical problem in metamaterial-based EC displays. Owing to its unique design, the metamaterial-based EC device achieves good color quality with no drop in brightness or shift in color chromaticity when compared with a single electrode. Moreover, the porous-metamaterial-based EC device can exhibit non-iridescence and be viewed from a wide range of angles (5°-85°) and has fast switching response (2.4 and 2.5 s for coloration and bleaching, respectively), excellent cycling performance (at least 2000 cycles), and extremely low power consumption (4.0mWcm-2 ).

Photonic crystal cavities having a wavelength-sized volume exhibit a strong light-matter interaction, which makes possible all-optical switches operating with ultralow energy consumption.Using the combination of an extremely small photonic crystal nanocavity and strong carrier-induced nonlinearity in InGaAsP, we have successfully demonstrated low-energy switching in the attojoule range for the first time.This switching energy is more than two orders of magnitude lower than that of previously reported optical switches.The ultrasmall cavity also contributes to fast carrier diffusion and hence a fast switching response of 20 ps at minimum.These all-optical switches with their small size and low-energy, fastresponse operation may open up the possibility of a dense photonic network on a chip.

We demonstrate a very simple electrically assisted technique for broad-range tuning of whispering gallery modes in microtube resonator, which is fabricated by embedding a FeCrAl heating wire with small resistance into a tapered silica microtube. The huge Joule heat generated by the heating wire can be effectively and thermally conducted to the microtube and consequently changes the path of the optical whispering gallery modes due to the thermo-optic effect. Experimental results show that such a device has a tuning range of 0.57 nm with excellent stability under the applied current of 200 mA, fast response (<;100 ms), and low power consumption (~0.1 mW). This makes it to have potentials in tunable filters or fast optical switches.

In this paper a novel lateral trench insulated-gate bipolar transistor with shorted trench anode (STA -LTIGBT) on Silicon-on-insulator (SOI) is proposed and discussed. Its main features of the proposed structure are the deep oxide trench in drift region and the trench anode design. Hence the proposed structure could reduce drastically the total chip area not only in the drift region but also in anode region. Numerical simulation results indicate that the proposed STA -LTIGBT structure could suppress the snapback effect commendably. Furthermore, it is shown that the turnoff time of the proposed structure is decreased by 84% compared to that of the conventional LTIGBT, and by 70% compared to that of the deep trench LTIGBT.

The use of an insulated-gate bipolar transistor (IGBT) to improve the switching performance of a gate turn-off (GTO) thyristor in a cascode switch is documented. The IGBT-gated GTO-cascode switch features simple drive requirement, fast switching, robustness, and overcurrent protection. The cascode switch was applied in a quasi-resonant buck power converter and simulated on a computer using PSpice. The IGBT-gated GTO-cascode switch is suitable for high-power (1200 V, 140 A) and high-frequency operation up to 30 kHz. The turn-off time of the main switch, GTO, is reduced significantly due to the reverse current gain of unity in cascode configuration.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

NbOx materials have shown considerable potential for the applications of artificial neurons due to their volatile threshold switching (TS) behavior, fast switching speed, and low power consumption. The TS can be attributed to its negative differential resistance (NDR) effect associated with heat accumulation. Experimental data show that the degradation of a NbOx-based neuron device is manifested by the shift in transition voltages, including threshold and hold voltages, and shrinkage in the voltage window. This problem strictly undermines the device reliability, and meanwhile, the mechanism is yet to be confirmed. In this work, a physical model involving the role of oxygen vacancies (Vos) is developed to further elucidate the TS behavior in NbOx-based devices. For the first time, a continuous drift of the operation voltages upon unipolar biases is simulated and attributed to the redistribution of Vos. We propose and experimentally demonstrate an efficient method that can mitigate the Vo migration problem, leading to a great improvement in the device endurance. Our developed model is not only closer to the real nature of the TS process in NbOx but can also provide more insight into the performance optimization of this important class of devices.

In deep sub-micron technologies, conventional silicon-based transistors are faced main several problems related to the short-channel effects such as power dissipation, subthreshold leakage, and drain-induced barrier lowering (DIBL). Graphene nano-ribbon field-effect transistors (GNRFETs) have become a potential contender as a substitute for traditional silicon-based transistors in next generation nano-electronic devices. They exhibit fantastic properties such as high charge carrier mobility, mean free path of electrons, faster switching, and high ION/IOFF ratio. In order to prove the competences and superiority of these types of transistors, various circuits like full adder (FA) cells, which are the main building block of computational systems must be simulated and studied. This paper presents redesigning various 1-bit FA cells such as Complementary Metal-Oxide-Semiconductor (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission-Gate (TG), Hybrid CMOS (HCMOS), and Transmission Function Adder (TFA) using MOS-GNRFET devices in 16nm technology node. Different HSPICE simulations are performed to obtain propagation delay, average power consumption, power-delay-product (PDP), and energy-delay-product (EDP) of FA cells and are compared with 16nm CMOS predictive technology model (PTM) at different supply voltages. The obtained results indicate that MOS-GNRFET based 1-bit FA cells have better performance than that of Si-CMOS one. The MOS-GNRFET based FA cells improve propagation delay and EDP at least 31.195% and 4.372%, respectively.

When a permanent magnet synchronous motor runs at low speed, the inverter will output discontinuous current and generate torque ripple; when the motor is runs at high speed, a large amount of stator harmonic current generates, which affects its speed following ability and torque stability. To ensure the fast and smooth switching of a permanent magnet synchronous motor in the full speed domain, this paper proposes the nonsingular terminal sliding mode control of PMSM speed control based on the improved exponential reaching law. Firstly, the improved exponential reaching law is composed of the state variables and power terms of the sliding mode surface functions. The reaching law function is designed in sections to balance the fast dynamic response of the system and chattering control. Secondly, an improved exponential reaching law based on the sliding mode control strategy of the PMSM speed loop is proposed. By designing the initial value of the integral term in the nonsingular terminal sliding mode surface function, the initial state of the system is located on the sliding mode surface. The integral sliding mode surface is used to reduce the system steady-state error, while the proposed sliding mode reaching law is used to increase the arrival speed and suppress system chattering, ultimately affecting modeling error problems, complex working conditions, and uncertainty factors. This paper proposes a sliding mode observer based on an improved exponential reaching law to compensate for the disturbances. Lyapunov stability theory can prove that this system can make the speed tracking error converge to zero in finite time. Hardware-in-the-loop experiments were used to validate the effectiveness of the proposed method.