Fault coverage analysis for physically-based CMOS bridging faults at different power supply voltages

Transistor level models and testing methodologies are developed for detecting the bridging faults in CMOS and BiCMOS circuits. The quiescent power supply current (IDDQ) is utilized as the basis of modelling and test generation. Multiple and single bridging faults are covered. Modelling and testing techniques are presented. The first technique employs a new model called the Current Transfer Function (CTF) that is used to detect the bridging faults in CMOS and BiCMOS circuits. The CTF is a Boolean representation of the IDDQ flow path in terms of input variables and transistor topology of a circuit. The other technique employs an extension of the logic transistor function (LTF) model that was developed earlier for detection of transistor stuck faults. This technique is used for modelling and generating the test for single bridging faults in CMOS circuits, as it is simpler and efficient. However, because of certain limitations this technique is not extended for bridging faults in BiCMOS circuits and the multiple bridging faults in CMOS circuits. The CTF and LTF are automatically generated by the path algebra technique.

Improvement of diagnosis methodologies is a key factor for fast failure analysis and yield improvement. As bridging defects are a common defect type in CMOS circuits, diagnosing this class of defect becomes relevant for present and future technologies. Bridging defects cause two additional current components, the bridge and the downstream current. This work presents the effect of the downstream current on current signatures and its impact on the diagnosis of such defects. The authors demonstrate that the impact of downstream current is minimized at low power supply (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> ) values. Therefore, current measurements at low power supply voltages are proposed to enhance bridge diagnosis. Experimental evidence of this behaviour is presented for real devices. Furthermore, current signatures measured at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VLV</sub> are used for the diagnosis of fifteen failing 0.18mum technology devices, which are demonstrated to contain a bridging defect.

Recently, it has been recognized that logic testing is very inefficient to detect physical defects in CMOS circuits. Most of the physical defects are modeled as bridging and open faults, which are not detected using a stuck-at fault model. In this study, we examined the detect efficiency of stuck-at test sets for bridging faults in Iddq environment. Our stuck-at test vectors are generated by standard ATPG programs. These test vectors are applied while power supply current is monitored. A high current state in the circuit is considered as a presence of a fault. Sets of combinational and sequential circuits are used in this study. The results are given in terms of intra-transistor and gate-level bridging fault coverages. >

As feature sizes of integrated circuits continue to shrink and demand for low power operation continues to increase, power supply voltages may eventually be reduced to the level where noise becomes significant compared with signals. This would cause digital logic circuits to exhibit non-deterministic behavior. In this paper, we study the stochastic behavior of simple digital circuits operating at low power supply voltages. We develop a method for modelling the stochastic behavior of circuits and apply the method to a CMOS inverter. We use numerical simulations of stochastic differential equations to obtain time- domain transient analysis of the CMOS inverter and magnitude statistics from multiple sample paths. Further, we derive the output distribution at steady state from first principles. We characterize the switching error and the information transmission based on the output steady state distribution. This study provides a detailed understanding of how noise affects the operation of the CMOS inverter at low power supply voltages. The method we develop here can also be extended to other circuits where stochastic sample paths and sample statistics are necessary to characterize the circuits. Traditional frequency domain noise analysis is not adequate to provide this information.

In the field of VLSI testing, fault diagnosis has become necessary. Though there are different types of faults available, the two commonly used faults are bridging and stuck-at faults. The methods that already exist involve the manual modification of the logical circuit like the addition of gates, multiplexers etc. The proposed work is about creating a pattern generation procedure for distinguishing between stuck-at and bridging faults without altering the circuit under test. The faults are considered in pairs and test patterns are generated accordingly to distinguish between the two faults using ATPG tools. The fault inactivation method has been used to generate the test patterns. Diagnosis patterns are generated that will be capable of individually distinguishing each fault pair in the circuit. Experiments have been conducted on the ISCAS’ 85 benchmark circuits and the number of diagnosis patterns obtained for each fault pair were tabulated. Other important parameters like the number of faults detected, fault coverage, CPU run time etc. were also analysed.

Many of the physical defects in CMOS circuits such as bridging and transistor stuck-on faults are not guaranteed to be detected by logic testing. In this paper, we examine the detection efficiency of stuck-at tests in covering all possible bridging faults in I/sub DDQ/ environment. We generate stuck-at fault test vectors for combinational and sequential benchmark circuits using standard ATPG programs. The circuits are simulated with these vectors and power supply current was monitored for bridging faults. A high current state in a faulty circuit is considered as an indicator of fault detection. The test results are given in terms of intra-transistor and gate-level bridging fault coverage. Our results show that stuck-at test vectors can be used very efficiently for I/sub DDQ/ testing of bridging faults, and extra effort to generate specialized test vectors may be unnecessary. >

Test application at reduced power supply voltage (or VLV testing) is a cost-effective way to increase the defect coverage of a test set. Resistive short defects are a major contributor to this coverage increase. Using a probabilistic model of these defects, we quantify the coverage impact of VLV testing for different voltages. When considering the coverage increase, we differentiate between defects missed by the test set at nominal voltage and undetectable defects (flaws) detected by VLV testing. In our analysis, the performance degradation of the device caused by lower power supply voltage is accounted for. Furthermore, we describe a situation in which defects detected by conventional testing are missed by VLV testing and quantify the resulting coverage loss. We report the numbers on the increased defect coverage, flaw coverage, and coverage loss for ISCAS circuits.

This paper presents accurate fault models, an accurate fault simulation technique, and a new fault coverage metric for resistive bridging faults in gate level combinational circuits at nominal and reduced power supply voltages. We show that some faults have unusual behavior, which has been observed in practice. On the ISCAS85 benchmark circuits we show that a zeroohm bridge fault model can be quite optimistic in terms of coverage of voltage-testable bridging faults.

We investigate a characterization of hard-to-detect bridging faults. For circuits with large numbers of lines (or nodes), this characterization can be used to select target faults for test generation efficiently, when it is impractical to target all the bridging faults (or all the realistic bridging faults). We demonstrate that the faults selected based on the proposed characterization are indeed hard-to-detect by performing the following experiments. 1) We show that the fault coverage of a given test set, with respect to the selected subset of bridging faults, is lower and more sensitive to the test set than the fault coverage obtained with respect to a random subset of bridging faults of the same size, with respect to the complete set of bridging faults, and when possible, with respect to a subset of realistic bridging faults of the same size. 2) We demonstrate that a test set generated for the selected subset of bridging faults detects other bridging faults more effectively than when a test set is derived for a randomly selected subset of bridging faults of the same size. We also describe an efficient procedure for selecting hard-to-detect bridging faults according to the proposed characterization. This procedure avoids enumeration of all the faults in order to select the hard-to-detect ones. This is important for large circuits where even enumeration of all the bridging faults may not be feasible.

Sense Amplifier is one of the major circuits in CMOS nonvolatile memories. The aim of this research is to implement Sense Amplifier in 0.18µm CMOS process to achieve both the lower reading power and superior reliability for sensing operation. In RFID transponder, EEPROM are used to store data. Memory access time, power dissipation and the reliability of an EEPROM is vigorously influenced by the features of the SA. Current type SA experience the larger current or power dissipation problems, which is not suitable for low voltage applications of RFID transponder. The proposed voltage-type SA is able to execute under a very low power supply voltage (VDD) between 1V to 2.6V VDD. The SA circuit implemented within the temperature range from -25 0 C to 125 0 C. The compact layout design has been carried out to evaluate the efficiency of the circuit. The modified low voltage-type SA is appropriate for low-voltage applications like RFID EEPROM. Ill. 6, bibl. 10, tabl. 1 (in English; abstracts in English and Lithuanian). DOI: http://dx.doi.org/10.5755/j01.eee.120.4.1466

Detection of transistor stuck-open faults in CMOS circuits requires two-pattern tests. Transition delay fault model is commonly used to model delay causing defects and it also requires two-pattern tests. In this paper we examine the relationship between the two fault models and propose a method for generating test patterns that achieve maximum coverage of both faults. In the proposed method we use an ATPG program for transition delay faults to generate test patterns for both faults. Experimental results are presented to evaluate the effectiveness of our approach.

A novel algorithm for diagnosing bridging faults in combinational circuits is presented. The voting model is assumed. The diagnosis algorithm guarantees the object bridging (bridging fault in the circuit being diagnosed) to be in the final fault list. The novelties of the algorithm are: (i) unlike previous algorithms it does not use the full fault dictionary but uses portions of the stuck-at fault dictionary which is computed dynamically; (ii) it enumerates the faults implicitly using a compact data structure; and (iii) fault dropping rules, using stuck-at fault simulation only, are used. The resulting algorithm is both time and space efficient. Experimental evaluation of the algorithm is presented.

The stuck-at fault model, which is commonly used with fault simulation, does not adequately evaluate the effects of bridging faults (shorts between adjacent signal lines) in CMOS circuits. Tests for bridging faults can be performed on automatic test equipment, and the test vectors can be evaluated using logic simulation.

Low supply voltage testing has traditionally been reported as an advantageous technique in detecting resistive bridging defects in combinational CMOS circuits. However, under certain topological conditions, the opposite effect is observed. These conditions are analysed. Applicability to diagnosis of bridging defects is discussed.

This paper presents two new circuit topologies of dc bus line series active snubber assisted soft switching PWM full-bridge dc-dc power converter acceptable for either utility ac 200 V-rms or ac 400 V-rms input voltage source. One of proposed power converters is composed of a typical voltage source full-bridge high frequency PWM inverter using dc bus line side series switching devices with the aid of a parallel capacitive lossless snubber. All the active power switches in the full-bridge arms and dc bus line can achieve ZCS turn-on and ZVS turn-off commutation operation and consequently the total turn-off switching losses can be significantly reduced. As a result, a high switching frequency for used IGBTs can be actually realized more than about 20 kHz. It is proved that the more the switching frequency of full-bridge inverter increases, the more soft switching PWM dc-dc power converter with a high frequency transformer link has remarkable advantages for its power conversion efficiency and power density as compared with the conventional hard switching PWM inverter type dc-dc converter. The effectiveness of this new converter topology is proved for low voltage and large current dc-dc power supplies as arc welding machine from a practical point of view