Fault coverage analysis of selection circuit based BIST for RF CP-PLL

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

Based on the model of SMIC 0.13 mixed-signal process and its supply voltage is 3.3 V, a Charge Pump Phase-Locked Loop is designed in this paper. The Verilog-A language is applied to build the behavioral modeling for the Charge Pump Phase-Locked Loop, in the bias circuit of Charge Pump a voltage regulation NMOS is added to reduce the charging and discharging current mismatch to less than 0.073%, and the design parameters of the Loop Low-Pass Filter is given in this paper. The Cadence simulation results show that the frequency of the input of the Charge Pump Phase-Locked Loop is 3~160MHz, and the output frequency is 3~400MHz; the maximum division number is 32 and the lock time is less than 22us.

Analog-mixed signal (AMS) circuits are widely used in various mission-critical applications necessitating their formal verification prior to implementation. We consider modeling two AMS circuits as hybrid automata, particularly a charge pump phase-locked loop (CP-PLL) and a full-wave rectifier (FWR). We present executable models for the benchmarks in SpaceEx format, perform reachability analysis, and demonstrate their automatic conversion to MathWorks Simulink/Stateflow (SLSF) format using the HyST tool. Moreover, as a next step towards implementation, we present the VHDL-AMS description of a circuit based on the verified model.

The analysis of the behavior of Charge Pump Phase-Locked Loop (CP-PLL) is a challenging task due to its mixed-signal architecture. Out of its two types, i.e. Current Switched CP-PLL (CSCP-PLL) and Voltage Switched CP-PLL (VSCP-PLL), the prior produces symmetrical pump currents, resulting in an appropriate transient performance to be analyzed. The loop parameters are important to set the gain, target frequency, and assure the stability of the system. The more important is the bandwidth of the loop, which is dependent on the loop filter parameters to perform stable operation and locking time. In this paper, the impact of loop parameter variations on the overall transient behavior of the system is investigated. It has been shown that loop parameters play an important role to ease the design of mixed-signal PLLs.

Analog and mixed-signal circuit testing is a challenging task demanding large amounts of resources. In order to battle against this drawback, alternate testing has been established as an efficient way of testing analog and M-S circuits by using indirect measures instead of the classic specification based testing. In this work we propose the use of Kendall's Tau rank correlation coefficient for rating the suitability of a set of candidate indirect measures to be used in mixed-signal testing. Such criterion is shown to be adequate since it allows to avoid or minimize information redundancy in the measures set. As a proof of concept, a 4th order band-pass Butterworth filter has been simulated under the presence of process variations. The circuit has been tested using a subset of measures selected according to minimum Kendall's Tau coefficient. Analog test efficiency metrics are reported showing test misclassification rate is among the best 15% possible, therefore validating the proposal.

Nondestructive Testing (NDT) methods provide scientists a way to understand the properties of samples without causing them damage. For an electrochemical device, it is crucial to investigate the behavior of it before, during, and after its operation. Therefore, NDT methods are indispensable for studying such devices.Literature highlights the effectiveness of elastic-wave-based testing methods in the evaluation of electrochemical devices. The Acoustic Emission (AE) method was applied to respectively study the behavior of Solid Oxide Fuel Cells (SOFCs) and Ni-MH batteries, while the Ultrasonic Testing (UT) method was applied to study Li-ion batteries. In our previous research, the signals representing cracking and delamination in SOFCs were successfully distinguished by their peak amplitude, wave shape, and AE energy [1]. The same technique was further used for the evaluation of mechanical damages in SOFCs during the operation [2]. In another study, similarly, the pulverization of the Ni-MH battery electrodes was observed by the AE technique, and frequency peak property was included in the discussion to classify the signals [3]. The UT method was employed to study the relationship between the state of charge of Li-ion batteries and the profiles of ultrasonic waves at different frequencies. The evolution of wave velocity, attenuation, and amplitude were discussed [4]. Based on these researches, elastic-wave-based testing methods are adopted by us.In our present study, the multi-frequencies in-situ ultrasonic monitoring technique was employed to analyze the behavior of the commercial Ni-MH batteries during the operation. Continuous ultrasonic waves at three different frequencies were separately sent into the specimens during charge cycles, and their waveforms were recorded and compared. Specific wave patterns were found near the end of the charge and discharge state, especially from the wave profiles at 750 KHz. The result showed that the evolution of waveform is frequency-dependent, which was also suggested in the literature [4]. Potential explanations for these wave patterns were inferred, including phenomena such as crystal structure evolution, internal pressure shift, and reverse of electrodes.Based on this finding, a new ultrasonic testing/monitoring method considering frequency analysis is also designed. In this new method, signals consisting of elastic waves at a wide range of frequencies with equal intensities are designed to be applied to various electrochemical devices. The application of this method will be included, while the frequency-dependent property of the testing of electrochemical devices will be assessed in combination with the present findings in this study.

Water quality testing is crucial for protecting public health, especially considering the number of boil water advisories annually issued across Canada that impact daily life for residents in affected areas. To overcome these challenges, the development of drinking water safety plans and accessibility to regular testing using simple, rapid, and accurate materials are necessary. However, the significance of monitoring the accuracy of environmental microbiology testing laboratories cannot be overlooked. Participation in external quality assessment programs, such as those that include proficiency testing (PT), is a necessary risk management resource that ensures the effectiveness of these testing processes. Proficiency Testing Canada (PTC), in collaboration with the Canadian Microbiological Proficiency Testing (CMPT) program based at the University of British Columbia, have implemented a drinking-water microbiology PT program since 1996. Both PTC and CMPT are ISO/IEC 17043:2010-accredited EQA providers. The drinking water program provided PT challenges to subscribing testing laboratories twice per year. Each challenge consisted of four samples containing unknown concentrations of Escherichia coli (E. coli) and Enterobacter spp. Results from participants were assessed for accuracy based on the method of testing. This cross-sectional study evaluated 150 rural and metropolitan testing sites across Canada between 2016 and 2022. Multivariable logistic regression analysis was conducted to examine the impact of different testing methods and laboratory accreditation status on the proficiency scores. This approach enabled us to assess the association between multiple independent variables and the likelihood of achieving specific proficiency scores, providing insights into how testing methods and accreditation status affect overall performance. After adjusting for rural residence, testing time, and survey year, the membrane filtration method was positively associated with the likelihood of scoring satisfactory results compared to the enzyme-substrate method (OR: 1.75; CI: 1.37-2.24), as well as accreditation status (OR: 1.47; CI: 1.16-1.85). The potential for improvement in environmental laboratory testing performance through the implementation of regulated PT in drinking water safety plans is proposed, along with the need for reliable testing methods applicable to rapid drinking water microbiology testing.

Systematic scenario test case generation for nuclear safety systems

Feasibility investigation of the mechanical behavior of methane hydrate-bearing specimens using the multiple failure method

Classical test pattern generator (TPG) only concern about producing maximum length of test vector. It does not consider the previous (history) of test vectors which have been generated in producing next test vectors. As a result, succeeding test vector may capture the same fault which resulted in low accumulated fault coverage. In this paper we introduced a new approach for testing both combinational circuits and sequential circuits with the aim to highlight on the importance to consider previous test vectors which have been generated in trying to capture different faults as the generation proceeds to produce consequence test vector. The proposed test method also manages to produce high fault coverage even though the test was sampled early without the need to wait till the last clock. Several experiments have been carried out on ISCAS benchmarks circuit and the results were compared with different test methods. The proposed test method proved effective, producing high fault coverage with a limited number of test vectors.

Field programmable gate arrays (FPGAs) have drawn wide attention from nuclear power industry for digital instrument and control applications (DI&C), because it’s much easier and simpler than microprocessor-based applications, which makes it more reliable. FPGAs can also enhance safety margins of the plant with potential possibility for power upgrading at normal operation. For these reasons, more and more nuclear power corporations and research institutes are treating FPGA-based protection system as a technical alternative. As nuclear power industry requires high reliability and safety for DI&C Systems, the development method and process should be fully verified and validated. For this reason, to improve the application of FPGA in NPP I&C system, the specific test methods are critical for the developers and regulators. However, current international standards and research reports, like IEC 62566 and NUREG/CR-7006, which have demonstrated the life circle of the development of FPGA-based safety critical DI&C in NPPs, but the specific test requirements and methods which are significant to the developers are not provided. In this paper, the whole test process of a pressurized water reactor (PWR) protection sub-system (Primary Coolant Flow Low Protection, Over Temperature Delta T Protection, Over Power Delta T Protection) is described, including detail component and integration tests. The Universal Verification Methodology (UVM) based on System Verilog class libraries is applied to establish the verification test platform. All these tests are conducted in a simulation environment. The test process is driven by the test coverage which includes code coverages (i.e., Statement, Branch, Condition and Expression, Toggle, Finite State Machine) and function coverage. Specifically, Register Transaction Level (RTL) simulation is conducted for Component tests, while RTL simulation, Gate Level simulation, Timing simulation and Static timing analysis are conducted for the integration test. The issues (e.g., the floating point calculation, FPGA resource allocation and optimization) arose in the test process are also analyzed and discussed, which can be references for the developers in this area. The component and integration tests are part of the Verification and Validation (V&V) work, which should be done by the V&V team separated from the development team. The testing method could assure the test results reliable and authentic. It is practical and useful for the development and V&V of FPGA-based safety DI&C systems.

This paper presents the current work that is done in order to simulate analog or mixed-signal tests and then transfer these simulations and their results to the ATE. After having stated the problem, the proposed flow will be reviewed, leading to a more detailed description of the VHDL-AMS simulations, of the STIL-AMS language under definition, as well as to its road map. One of the major decisions taken, a device-centric approach versus a tester-centric approach, will then be explained, before showing some of the actual limitations of the approach. Before concluding, the real case that has been implemented will be described, and some of the debug steps that have been done

One of the key new features of connected lighting systems (CLS) is their ability to collect data from various types of integral sensors and share that data with other lighting or building systems. Occupancy and vacancy sensors have been widely adopted as an energy-saving strategy in buildings, yet published test methods for reproducibly characterizing their performance remain few and limited in their sophistication. As a result, it has been difficult to predict the performance of such sensors in a specific application, and in practice, they frequently do not meet energy-savings expectations. Occupants at times remove or otherwise bypass occupancy sensors that hinder their work or otherwise do not perform as expected, thereby compromising the sensors’ potential to reduce energy consumption. Poor performance can result from multiple causes – ranging from fundamental limitations of the sensor technology, to misconfiguration, to poor placement in the room or space. Innovative occupancy sensors, some of them combining multiple sensing technologies (i.e., multimodal), have come on the market over the years, with claims of improved performance compared to their predecessors. However, in practice, their performance has neither differed enough from the performance of previous products to necessitate a test method that facilitated comparison between them, nor has it led to high deployment or high user satisfaction in human-occupied spaces with persistent presence. While the performance of both common and novel occupancy sensors has been the subject of many published research articles, the test methods that have been employed for them typically have been loosely described and have incorporated custom equipment or techniques that render them difficult to reproduce, or have been limited in their ability to fairly characterize devices that utilize varying sensor technology. The lack of a fully described, technology-agnostic test method that yields reproducible results across different implementations has been a barrier to the commercial success of new occupancy-sensor products, as users and specifiers who have been disappointed with previous products are often unwilling to take a chance with new ones. Motivated by a desire to fairly characterize new technologies that continue to enter the market and claim not only improved occupancy detection but, in some cases, additional capabilities (e.g., the ability to measure traffic or discern between different object types), this report presents the results of a literature review of recently published fully described test methods for characterizing occupancy-sensor performance, as well as research articles containing ad-hoc test methods. The review also identifies and consolidates test conditions for characterizing sensor performance in indoor spaces and identifies apparent test method gaps that need to be filled in order to evaluate emerging technologies and products. The identified test-method conditions are intended to enable the development of a future technology-agnostic test method that facilitates occupancy-sensor performance characterization more-accurately representing performance in buildings.

One of the critical approaches for scale control is the proper selection and use of scale inhibitors. Laboratory tests help to select the appropriate scale inhibitor with the most common testing methods, including static bottle test and dynamic scaling loop test. Recently, Kinetic Turbidity Test (KTT) has gained increased recognition as a new testing method for scale inhibitor evaluation due to short testing time, simple sample preparation, and good reproducibility. There has been a good deal of research and studies on KTT as a technique for multifunctional scales, including calcium carbonate and barium sulfate (especially low scaling brines), halite and silicates. In addition, KTT can examine dispersant effects of polymers and surfactants on scale and other solids and can work under anaerobic conditions to give mechanistic understanding in the presence of iron. This paper discusses an alternative and efficient scale inhibitor testing method and gives insight for scale treatment chemistry and dosage by comparing and contrasting the different evaluation methods for scale inhibitors.

A continuous-time phase frequency detector (PFD) based on the conventional tri-state PFD is proposed for fast lock charge pump phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be substantially reduced with the proposed continuous-time scheme. During the period that the best tracing and acquisition properties are required, the bandwidth of the PLL can be increased to decrease the locking time with the proposed continuous-time PFD. Afterwards, the bandwidth of the PLL is recovered to the original value to minimize output jitter due to external noise. Any conventional tri-state PFDs can be improved with the proposed continuous-time architecture. The proposed architecture is realized in a standard CMOS 0.35 mum technology. The simulation results demonstrate that the proposed continuous-time PFD is effective to get more speedy locking time.