Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration

Heterogeneous manycore architectures are the key to efficiently execute compute- and data-intensive applications. Through-silicon-via (TSV)-based 3D manycore system is a promising solution in this direction as it enables the integration of disparate computing cores on a single system. Recent industry trends show the viability of 3D integration in real products (e.g., Intel Lakefield SoC Architecture, the AMD Radeon R9 Fury X graphics card, and Xilinx Virtex-7 2000T/H580T, etc.). However, the achievable performance of conventional TSV-based 3D systems is ultimately bottlenecked by the horizontal wires (wires in each planar die). Moreover, current TSV 3D architectures suffer from thermal limitations. Hence, TSV-based architectures do not realize the full potential of 3D integration. Monolithic 3D (M3D) integration, a breakthrough technology to achieve “More Moore and More Than Moore,” opens up the possibility of designing cores and associated network routers using multiple layers by utilizing monolithic inter-tier vias (MIVs) and hence, reducing the effective wire length. Compared to TSV-based 3D integrated circuits (ICs), M3D offers the “true” benefits of vertical dimension for system integration: the size of an MIV used in M3D is over 100 × smaller than a TSV. This dramatic reduction in via size and the resulting increase in density opens up numerous opportunities for design optimizations in 3D manycore systems: designers can use up to millions of MIVs for ultra-fine-grained 3D optimization, where individual cores and routers can be spread across multiple tiers for extreme power and performance optimization. In this work, we demonstrate how M3D-enabled vertical core and uncore elements offer significant performance and thermal improvements in manycore heterogeneous architectures compared to its TSV-based counterpart. To overcome the difficult optimization challenges due to the large design space and complex interactions among the heterogeneous components (CPU, GPU, Last Level Cache, etc.) in a M3D-based manycore chip, we leverage novel design-space exploration algorithms to trade off different objectives. The proposed M3D-enabled heterogeneous architecture, called HeM3D , outperforms its state-of-the-art TSV-equivalent counterpart by up to 18.3% in execution time while being up to 19°C cooler.

Monolithic inter-layer vias (MIVs) used in 3D integration technology are much smaller than through-silicon vias (TSVs) used in TSV-based 3D integration. Thus, monolithic 3D integration provides shorter wire length, better performance, and lower power consumption than TSV-based 3D integration. Multi-tier monolithic 3D integration stacks more than two silicon layers, thereby increasing the device density, which reduces the wire length and power consumption and improves performance further than two-tier monolithic 3D integration. Since the size of an MIV is comparable to that of a local via, the wire lengths of multi-tier gate-level monolithic 3D IC layouts are expected to be close to the ideal wire length reduction ratio, for example, 29, 42, and 50 percent for two-, three-, and four-tier designs, respectively. However, it is still unknown whether it would be possible to achieve the ideal wire length reduction ratios by multi-tier gate-level monolithic 3D integration. In this paper, we propose an efficient routing methodology to design multi-tier monolithic 3D ICs. Using the design methodology, we design two- to eight-tier gate-level monolithic 3D IC layouts and thoroughly investigate the wire length characteristics of the layouts. The simulation results show that the proposed routing methodology reduces the wire length by 12 to 53 percent compared to the 2D designs. In addition, the proposed routing methodology builds multi-tier monolithic 3D IC layouts more efficiently than a state-of-the-art methodology with comparable routed wire length.

Monolithic three-dimensional (3D) integration enables the most fine-grained integration of transistors by stacking very thin layers and fabricating monolithic inter-layer vias as small as local vias. Thus, monolithic 3D integration is expected to provide a higher degree of wirelength reduction, performance improvement, and power saving. Due to the prospective properties of the monolithic 3D integration technology, research on multilayer monolithic 3D integration that stacks more than two device layers is also ongoing. In this paper, we propose an algorithm that optimizes dynamic power consumption of gate-level monolithic 3D ICs. Under the same timing constraints, our algorithm reduces dynamic power consumption more effectively than a uniform-scaling-based placement algorithm. We also design multi-tier monolithic 3D ICs and show that our algorithm outperforms the uniform-scaling-based placement algorithm by 11.4% on average.

Monolithic three-dimensional (3D) integration enables revolutionary digital system architectures of computation immersed in memory. Vertically-stacked layers of logic circuits and memories, with nano-scale inter-layer vias (with the same pitch and dimensions as tight-pitched metal layer vias), provide massive connectivity between the layers. The nano-scale inter-layer vias are orders of magnitude denser than conventional through silicon vias (TSVs). Such digital system architectures can achieve significant performance and energy efficiency benefits compared to today's designs. The massive vertical connectivity makes such architectures particularly attractive for abundant-data applications that impose stringent requirements with respect to low-latency data processing, high-bandwidth data transfer, and energy-efficient storage of massive amounts of data. We present an overview of our progress toward realizing monolithic 3D ICs, enabled by recent advances in emerging nanotechnologies such as carbon nanotube field-effect transistors and emerging memory technologies such as Resistive RAMs and Spin-Transfer Torque RAMs.

Monolithic 3D (M3D) technology enables unprecedented degrees of integration on a single chip. The miniscule monolithic inter-tier vias (MIVs) in M3D are the key behind higher transistor density and more flexibility in designing circuits compared to conventional through silicon via (TSV)-based architectures. This results in significant performance and energyefficiency improvements in M3D-based systems. Moreover, the thin inter-layer dielectric (ILD) used in M3D provides better thermal conductivity compared to TSV-based solutions and eliminates the possibility of thermal hotspots. However, the fabrication of M3D circuits still suffers from several non-ideal effects. The thin ILD layer may cause electrostatic coupling between tiers. Furthermore, the low-temperature annealing degrades the top-tier transistors and bottom-tier interconnects. An NoC-based manycore design needs to consider all these M3D- process related non-idealities. In this paper, we discuss various design challenges for an M3D-enabled manycore chip. We present the power-performance-thermal trade-offs associated with these emerging manycore architectures.

Three-dimensional integration is a pivotal strategy for advancing the integrated circuit performance beyond traditional scaling limits. Herein, we report a monolithic 3D (M3D) integration technology using carbon nanotube (CNT) networks to fabricate four-layer complementary metal oxide semiconductor (CMOS) thin-film transistors (TFTs), representing the highest layer count to date for CNT-based CMOS M3D devices. The vertically stacked structure achieves enhanced integration density through layer-by-layer stacking with interlayer isolation via low-temperature-processed dielectrics, enabling the stable operation of N-type and P-type CNT-TFTs in separate layers. Functional IC units, including CMOS inverters and trans-impedance amplifiers (TIAs), were successfully implemented using this four-layer architecture. Furthermore, vertical integration of the M3D TIA with a molybdenum disulfide (MoS2) photodetector realized a monolithic optoelectronic sensing system, achieving primary amplification of photocurrents with a trans-impedance gain of 7.21 × 103 Ω. This work validates the feasibility of CNT-based M3D integration for high-density, multifunctional ICs and paves the way for next-generation optoelectronic systems and power devices.

Monolithic inter-tier vias (MIVs) in monolithic 3-D integrated circuits (M3D ICs) enables massive vertical integration. However, MIVs are more susceptible to defects due to high integration density and complex manufacturing processes. Existing MIV test techniques can effectively detect and locate MIV faults, but diagnosable fault types are limited. We propose a novel fault diagnosis method based on signal transmission performance analysis. This method can diagnose more fault types, including resistive open, hard open, short, and leakage faults. In the proposed solution, fault diagnosis can be carried out by comprehensively monitoring voltage and delay characteristics of MIVs. The effectiveness of fault diagnosis is verified through high speed simulation program with integrated circuit emphasis (HSPICE) simulations. We also perform Monte Carlo simulations to prove that the proposed method has high robustness even in the case of process variations. Experimental results show that the proposed method has low hardware overhead while ensuring high diagnostic resolution.

ABSTRACTIntegrating 2D materials into 3D architectures can break through the physical limits of materials in advanced processes. However, challenges such as severe interfacial doping caused by dielectric deposition during vertical stacking processing have led to performance degradation in MoS2 3D gate-all-around (GAA) field-effect transistors (FETs), thereby severely hindering their large-scale integration. Here, we demonstrate a lossless monolithic 3D (M3D) integration process flow enabled by using an interface engineering strategy to achieve the highly uniform large-scale integration of multichannel MoS2 GAAFETs with ultrahigh current density. This strategy involves reducing interface states and dielectric doping by forming van der Waals contacts with MoS2 and creating hydrophilic surfaces for high-κ dielectric deposition via an Sb2O3 layer, thereby significantly improving the performance of the GAAFETs. The statistics of 112 GAA devices exhibit record-breaking performance, including an average on-state current density of 227 μA/μm with a peak value of >335 μA/μm, and an ideal minimum subthreshold swing approaching 60 mV/dec, all outperforming conventional back-gate transistors and other MoS2 3D FETs. Furthermore, Technology Computer Aided Design simulation confirms that gate-all-around transistors exhibit a 46% reduction in resistance capacitance delay compared with planar structures, further demonstrating enhanced gate control. This work establishes a manufacturing pathway for achieving the interface-doping-free deposition of gate dielectric layers, thereby addressing the performance-degradation issue caused by repeated processing steps in high-density M3D heterogeneous integration.

Deep neural network (DNN) models are being expanded to a broader range of applications. The computational capability of traditional hardware platforms cannot accommodate the growth of model complexity. Among recent technologies to accelerate DNN, resistive memory (ReRAM)-based processing-in-memory (PIM) emerged as a promising solution for DNN inference due to its high efficiency for matrix-based computation. We face two major technical challenges in extending the use of ReRAM-based accelerators for training: (1) full-precision data is essential in back-propagation; (2) the need to support both feed-forward and back-propagation aggravates the data-movement burden. We propose a heterogeneous architecture named as 3D-ReG, which leverages full-precision GPU to ensure training accuracy and low-overhead 3D integration to provide low-cost data movements. Moreover, we introduce conservative and aggressive task-mapping schemes, which partition the computation phases in different ways to balance execution efficiency and training accuracy. We evaluate 3D-ReG implemented with two 3D integration technologies, through-silicon vias (TSVs) and monolithic inter-tier vias (MIVs), and compare them with GPU-only and PIM-only counterparts. Various GPU-only platforms using two main-memory technologies (DRAM, ReRAM) and three interconnect technologies (2D, TSV, MIV) are evaluated as well. Experimental results show that 3D-ReG can achieve on average 5.64× training speedup and 3.56× higher energy efficiency compared with the GPU with DRAM as main memory, at the cost of 0.05%–3.39% accuracy drop. We define a new metric, gain-loss ratio (GLR), which quantitatively evaluates the capability of a DNN training hardware in terms of the model accuracy and hardware efficiency. The results of our comparison show that the aggressive task-mapping scheme on MIV-based 3D-ReG outperforms the other methods.

Monolithic 3D (M3D) integration technology offers fine grain gate level stacking capability compared to 3D Through Silicon Vias (3D-TSV) which is well adapted for coarse-grain applications. As a result, design partitioning, i.e. Which cell on which tier, highly affects the 3D design performance. Previous partitioning methodologies focus on minimizing number of 3D interconnects for equal area ratio between the stacked partitions. This paper demonstrates that un-balancing the tier to tier area ratio of the M3D design brings better performance than classical balanced 3D design approach. Our study highlights that neither balanced area ratio nor the number of 3D interconnections remains mandatory criteria for M3D. We show that our technique can achieve up to 24% performance improvement compared to 2D and 15% better performance than the state-of-the-art technique without extra power penalty.

Three-dimensional (3D) monolithic integration can enable higher density and has the potential to stack independently optimized layers at transistor level. Owing to high mobility and lower processing temperatures, InGaAs is well-suited to be used as the top layer channel material in 3D monolithic integration along with Si/Si(Ge) FETs. A review of recent progress to develop InGaAs-on-Si(Ge) 3D Monolithic technology is presented here.

Heterogeneous monolithic 3D integration for hybrid vertical CMOS inverter using n-type IGTO TFT on p-type Si FET

Monolithic 3D ICs (M3D) are an emerging technology that offers an ultra-high-density 3D integration due to the extremely small size of monolithic inter-tier vias. We explore various design styles available in M3D and present design techniques to obtain GDSII-level signoff quality results for each of these styles. We also discuss various challenges facing each style and provide solutions to them.

As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

Recent advances in deep learning can be attributed to the continued performance improvement of hardware processors and artificial intelligence (AI) accelerators. In addition to conventional CMOS accelerators based on Von Neumann architecture, emerging technologies such as silicon photonics, memristors, and monolithic 3D (M3D) integration are being explored as post-Moore's law alternatives. However, the energy efficiency and performance of emerging AI accelerators can be catastrophically impacted by faults due to fabrication-process variations, thermal crosstalk, and aging. In this paper, we analyze the performance of several emerging AI accelerators in the presence of different uncertainties, and present low-cost methods to assess the significance of faults and mitigate their effects. We show that across all technologies, the impact of uncertainties on the performance can vary significantly based on the fault type and the parameters of the affected component. Therefore, the fault criticality-assessment techniques presented in this paper are necessary for yield improvement.