10- https://doi.org/10.1109/ats.2015.38
Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits
- Nov 1, 2015
- Kuan-Ying Chiang +4 more
Abstract
A FAST fault model is proposed for small delay faults induced by cross-gate defects in FinFET. FAST ATPG, fault simulation, and test selection are presented to generate and select test patterns to detect FAST faults. Experiments on large benchmark circuits show that our pattern sets have approximately 29% and 4% better FAST coverage and FAST SDQL respectively than those of commercial tool timing-unaware 1-detect pattern sets.
- # Fast Fault
- # Fault Simulation
- # FinFET Circuits
- # Fast Coverage
- # FAST Fault Simulation
- # Fault Test Pattern
- # Test Pattern
- # Pattern Sets
- # Defects In Circuits
- # Small Faults
