Fault Tolerant Computing Research.

Fault tolerance engineering has been advocated as one of the main approaches to ensuring the overall system dependability. The 2nd International Workshop on Engineering Fault Tolerant Systems (EFTS 2007) aims to investigate how fault tolerance mechanisms can be taken into account when engineering complex software systems and to improve our understanding of where and how fault-tolerance should be integrated in the software life-cycle. The focus of the workshop is on developing novel models to be applied at different abstraction levels (requirements, architecture and design models for fault tolerance, together with new implementation schemes), innovative technologies (tools and frameworks for implementing distributed fault tolerant systems) and advanced verification environments (to assess the achieved level of fault tolerance and to evaluate the dependability properties of the systems). Recently there has been a growing interest in the areas directly related and overlapping with fault tolerance, such as self-healing, resilience, self-adaptation and self-management. The topics related to engineering of systems with such properties are in the scope of the workshop as the intention is to improve the current understanding of how fault tolerance engineering can benefit from research on these areas.

FIFTEEN years ago, the term fault-tolerant computing made its first widespread appearance in the technical literature. In March of 1971, the Digest of the First International Symposium on Fault-Tolerant Computing appeared, followed in November by the First Special Issue on Fault- Tolerant Computing of the IEEE TRANSACTIONS ON COMPUTERS. More than any other, these two publications—the Digests of the FTC Symposia and the Special Issues on Fault- Tolerant Computing—have mirrored the advances in fault- tolerant computing over the last decade and a half. From over 100 submissions—a record high—received for this ninth Special Issue, 24 were selected for publication. These 9 papers and 15 correspondence items certainly continue this proud tradition.

Sun, J., 2020. Fault tolerance mechanism of distributed system for marine communication network. In: Gong, D.; Zhang, M., and Liu, R. (eds.), Advances in Coastal Research: Engineering, Industry, Economy, and Sustainable Development. Journal of Coastal Research, Special Issue No. 106, pp. 605–608. Coconut Creek (Florida), ISSN 0749-0208.When the communication network fails or the signal is interrupted, the distributed fault-tolerant system can continue to complete the communication task, which is needed to improve the fault-tolerant performance of the distributed system. Therefore, the key technologies of fault tolerance need to be studied, including the distributed fault-tolerant communication network simulation platform, the communication-network information-storage data structure, the communication protocol between communication network nodes, and the fault-tolerant algorithm of distributed communication network system. In the marine environment, the fleet exchanges data through wireless networks to understand the situation of the fleet-detection area, which can share the processing and calculation tasks. However, the marine environment is complex and changeable, which can cause great interference to the wireless signal, such as sea and cloud-rain clutter. These marine environments will cause the network communication signals to be greatly disturbed, which makes the distributed system unable to guarantee the communication interconnection between each node at any time. Therefore, a data-sharing and distributed-system platform needs to be built, which will design a reasonable system fault-tolerance mechanism. Through the fault-tolerance mechanism of the communication network system, the problem of frequent-node exits can be solved. By optimizing the fault-tolerant strategy of distributed architecture, the system's disaster resistance can be improved. In this research, a fault-tolerance mechanism for a distributed system was designed, which is more suitable for node election.

This paper shows that quantum computation can be made fault-tolerant against errors and inaccuracies when $\eta$, the probability for an error in a qubit or a gate, is smaller than a constant threshold $\eta_c$. This result improves on Shor's result [Proceedings of the 37th Symposium on the Foundations of Computer Science, IEEE, Los Alamitos, CA, 1996, pp. 56–65], which shows how to perform fault-tolerant quantum computation when the error rate $\eta$ decays polylogarithmically with the size of the computation, an assumption which is physically unreasonable. The cost of making the quantum circuit fault-tolerant in our construction is polylogarithmic in time and space. Our result holds for a very general local noise model, which includes probabilistic errors, decoherence, amplitude damping, depolarization, and systematic inaccuracies in the gates. Moreover, we allow exponentially decaying correlations between the errors both in space and in time. Fault-tolerant computation can be performed with any universal set of gates. The result also holds for quantum particles with $p>2$ states, namely, p-qudits, and is also generalized to one-dimensional quantum computers with only nearest-neighbor interactions. No measurements, or classical operations, are required during the quantum computation. We estimate the threshold of our construction to be $\eta_c\simeq 10^{-6}$, in the best case. By this we show that local noise is in principle not an obstacle for scalable quantum computation. The main ingredient of our proof is the computation on states encoded by a quantum error correcting code (QECC). To this end we introduce a special class of Calderbank–Shor–Steane (CSS) codes, called polynomial codes (the quantum analogue of Reed–Solomon codes). Their nice algebraic structure allows all of the encoded gates to be transversal. We also provide another version of the proof which uses more general CSS codes, but its encoded gates are slightly less elegant. To achieve fault tolerance, we encode the quantum circuit by another circuit by using one of these QECCs. This step is repeated polyloglog many times, each step slightly improving the effective error rate, to achieve the desired reliability. The resulting circuit exhibits a hierarchical structure, and for the analysis of its robustness we borrow terminology from Khalfin and Tsirelson [Found. Phys., 22 (1992), pp. 879–948] and Gács [Advances in Computing Research: A Research Annual: Randomness and Computation, JAI Press, Greenwich, CT, 1989]. The paper is to a large extent self-contained. In particular, we provide simpler proofs for many of the known results we use, such as the fact that it suffices to correct for bit-flips and phase-flips, the correctness of CSS codes, and the fact that two-qubit gates are universal, together with their extensions to higher-dimensional particles. We also provide full proofs of the universality of the sets of gates we use (the proof of universality was missing in Shor's paper). This paper thus provides a self-contained and complete proof of universal fault-tolerant quantum computation in the presence of local noise.

Fault tolerance in microprocessor systems has become a popular topic of architecture research. Much work has been done at different levels to accomplish reliability against soft errors, and some fault tolerance architectures have been proposed. But little attention is paid to the thread level superscalar fault tolerance. This letter introduces microthread concept into superscalar processor fault tolerance domain, and puts forward a novel fault tolerance architecture, namely, MicroThread Based (MTB) coarse grained transient fault tolerance superscalar processor architecture, then discusses some detailed implementations.

The realization of fault tolerant computers requires a considerable effort, both for their development and validation. In addition, the redundancy required to achieve the fault tolerance increases power consumption, mass and volume of the computers. In order to mitigate these problems, a standardized Fault Management Element (FME) has been developed, in which the complete set of fault management functions necessary to realize fault tolerant computers are provided once and for all in standardized and fully validated form. The fault management technology of this FME is based on the Byzantine fault tolerant computer for the Russian Service Module of the International Space Station, and for the logistics vehicle ATV servicing the station. Using this FME, fault tolerant computers need not be developed in the usual sense, but are basically realized by a configuration process, which, in simplified terms, comprises an integration of an FME with each of the foreseen redundant application processor boards, and their cross-strapping via the preconceived high-speed data links of the FMEs. By this novel approach the considerable development and validation effort to realize fault tolerant computers is practically eliminated. Moreover, the FME, which is currently available as printed circuit board, will be available as ASIC in the near future, such that the above mentioned power, mass and volume problems are also greatly reduced.

Considering the Internet of Things (IoT) impact in today’s world, uninterrupted service is essential, and recovery has received more attention than ever before. Fault-tolerance (FT) is an essential aspect of network resilience. Fault-tolerance mechanisms are required to ensure high availability and high reliability in systems. The advent of software-defined networking (SDN) in the IoT plays a significant role in providing a reliable communication platform. This paper proposes a data plane fault-tolerant architecture using the concepts of software-defined networks for IoT environments. In this work, a mathematical model called Shared Risk Link Group (SRLG) calculates redundant paths as the primary and backup non-overlapping paths between network equipment. In addition to the fault tolerance, service quality was considered in the proposed schemes. Putting the percentage of link bandwidth usage and the rate of link delay in calculating link costs makes it possible to calculate two completely non-overlapping paths with the best condition. We compare our two proposed dynamic schemes with the hybrid disjoint paths (Hybrid_DP) method and our previous work. IoT developments, wireless and wired equipment are now used in many industrial and commercial applications, so the proposed hybrid dynamic method supports both wired and wireless devices; furthermore multiple link failures will be supported in the two proposed dynamic schemes. Simulation results indicate that, while reducing the error recovery time, the two proposed dynamic designs lead to improved service quality parameters such as packet loss and delay compared to the Hybrid_DP method. The results show that in case of a link failure in the network, the proposed hybrid dynamic scheme’s recovery time is approximately 12 ms. Furthermore, in the proposed hybrid dynamic scheme, on average, the recovery time, the packet loss, and the delay improved by 22.39%, 8.2%, 5.66%, compared to the Hybrid_DP method, respectively.

Rapid growth of mobile usage and on demand applications not only requires huge performance enhancements of cellular network but also requires fault tolerance, cost effectiveness at its access sub network level. This paper proposes cost optimization model along with fault tolerance for cellular access network. The first objective of the problem is minimization of link cost by optimal assignment of base station to base station controller in a cellular access network, incorporating connectivity constraint and capacity constraint. The fault tolerant mechanism is that, the access network will be able to communicate even in case of any network failure. The second objective aims at fault tolerant mechanism to surmount transmission level link failure by using link redundant multi homing strategy. The mathematical mixed integer programming model has been used to formulate the problem. The fault tolerant cost optimization is a NP hard problem. Therefore simple and efficient heuristic algorithm targeting cost optimization along with fault tolerance has been proposed. The result achieves an average residual capacity of ~26% with back up link assignment. Further, load allocation during multi link failure is attained within minimum gap of 1%. The computation time almost remains same for single and multiple link failure. The algorithm performs well in both small and lager access network.

This article examines the functioning of sensor networks as a key component of the Internet of Things (IoT) technology, which facilitates integration between the physical and digital worlds. It analyzes the challenges sensor networks face, including limited resources, node failures, scalability, and security threats. The main components of sensor networks are discussed: sensors, smart elements, gateways, and communication modules that enable data collection and transmission for further analysis. Attention is drawn to the fact that sensor networks are often targets of malicious attacks, such as DDoS, Sinkhole, and routing attacks, which necessitate the development of new protection methods. The paper thoroughly examines threats from illegitimate elements in sensor networks that can disrupt network operations, cause data leaks, and affect network resilience and fault tolerance by exhausting resources. To effectively detect such nodes, it is proposed to apply mechanisms for traffic analysis, energy consumption monitoring, and encryption. The nature of failures in sensor networks and the interrelationship between fault tolerance and security are explored. Probabilities of failure for networks of different sizes are calculated, and mechanisms for improving fault tolerance, including node redundancy, self-healing algorithms, and fault tolerance mechanisms, are proposed. A methodology for detecting malicious nodes based on traffic and energy characteristics analysis is suggested. It was found that nodes exceeding threshold values for the number of transmitted packets or energy consumption may be malicious. It is noted that combining various methods will improve the accuracy of detecting malicious nodes at early stages, significantly enhancing the level of information security in sensor networks. Prospects for further research into the development of new protective mechanisms and improvements in the fault tolerance of sensor networks are highlighted.

Fog computing aims to provide the solution of bandwidth, network latency and energy consumption problems of cloud computing. Likewise, management of data generated by healthcare IoT devices is one of the significant applications of fog computing. Huge amount of data is being generated by healthcare IoT devices and such types of data is required to be managed efficiently, with low latency, without failure, and with minimum energy consumption and low cost. Failures of task or node can cause more latency, maximum energy consumption and high cost. Thus, a failure free, cost efficient, and energy aware management and scheduling scheme for data generated by healthcare IoT devices not only improves the performance of the system but also saves the precious lives of patients because of due to minimum latency and provision of fault tolerance. Therefore, to address all such challenges with regard to data management and fault tolerance, we have presented a Fault Tolerant Data management (FTDM) scheme for healthcare IoT in fog computing. In FTDM, the data generated by healthcare IoT devices is efficiently organized and managed through well-defined components and steps. A two way fault-tolerant mechanism i.e., task-based fault-tolerance and node-based fault-tolerance, is provided in FTDM through which failure of tasks and nodes are managed. The paper considers energy consumption, execution cost, network usage, latency, and execution time as performance evaluation parameters. The simulation results show significantly improvements which are performed using iFogSim. Further, the simulation results show that the proposed FTDM strategy reduces energy consumption 3.97%, execution cost 5.09%, network usage 25.88%, latency 44.15% and execution time 48.89% as compared with existing Greedy Knapsack Scheduling (GKS) strategy. Moreover, it is worthwhile to mention that sometimes the patients are required to be treated remotely due to non-availability of facilities or due to some infectious diseases such as COVID-19. Thus, in such circumstances, the proposed strategy is significantly efficient.

With the growing scale of high performance computing platforms and the increasing scientific computing demands, fault tolerance in MPI programs has become a major issue. This paper proposed an analytical performance model to help check pointing mechanisms to get better performance. In this paper, after the introduction of different fault tolerant mechanisms, we focus on the segment-level and variable-level check pointing approaches and analyze how the fault tolerant mechanisms affect the performance of current MPI systems, then we introduced the analytical performance model we proposed. Last we evaluated and analyzed the performance of two classic fault tolerant approaches and propose what should be done to advance variable-level check pointing mechanisms.

Currently, using commercial off-the-shelf (COTS) components and constructing parallel system becomes the main way to improve satellite system performance remarkably. System reliability relying on its structure rather than devices makes system fault-tolerant architecture and strategy increasingly important. As centralized fault-tolerant solution has the inherent drawback of single point of failure (SPOF), it can not guarantee system reliability well. Distributed fault- tolerant method, due to its complexity and large overhead, has not been maturely used. In this paper, we propose a new distributed fault-tolerant scheme with high reliability and flexibility, in which an equal symmetric distributed fault- tolerant (ESDFt) architecture is constructed. Based on the structure, functional module framework of system nodes and autonomous fault-tolerant strategy are designed. The ESDFt scheme creates favorable conditions for flexible implementation of system fault tolerance. It utilizes the master election mechanism, which eliminates the risks of SPOF and chooses master node intelligently based on user's configuration, making fault-tolerant complexity and processing overhead flexibly adjustable. The verification and evaluation of ESDFt scheme has been performed on a prototype system. The experiment results prove that ESDFt scheme not only ensures system reliability well, but also enhances system flexibility and practicality at the same time.

Fault tolerance is the most imperious issue in the cloud to provide reliable services. Inherent vulnerability to failure hampers the performance and reliability of cloud services. Hence, to achieve reliability, fault tolerance becomes a mandatory feature which is hard to implement due to the dynamic infrastructure and complex interdependencies. Numerous fault tolerance techniques have been developed in the literature to address the challenges of cloud reliability. A recent research survey presented in this paper attempts to integrate the different fault tolerance architecture. This study presents a critical research review on various existing fault tolerance techniques to improve services reliability, availability, and applications execution in the cloud. A comparative analysis, based on different critical metrics like failure prediction, detection strategy, failure history, VM placement, and limitations, of the reviewed framework systems is also included in the paper. This review intends to facilitate the development of the new fault tolerance technique for the cloud environment.

Summary form only given. The proliferation of new terminals represents a major growth factor for the semiconductor industry. Multimedia mobile phones, game consoles, digital TV sets combine previously separated products and functions into a single box, often built around a single chip. This convergence of devices that integrate storage, security, multimedia, mobility, connectivity and computing on the same piece of silicon represents an enormous growth opportunity for the global semiconductor industry and is focused on consumer architectures. In this scenario, the reliability of semiconductor devices represents a key issue, where the driving factors are the increasing miniaturization of process lithography, the mechanical shocks to which handheld terminals are subject, the usage of new materials due also to environmental regulations, the shorter time-to-market and the demand for low-cost components. New issues come from the advent nanometric devices: defect and fault tolerance -at the physical, circuit and most importantly at the system level- is an enabling technology for building reliable nanoelectronic systems. Semiconductor manufacturers are responding to these challenges by introducing a variety of technical innovations, including new manufacture testing methodologies, virtual testing, prediction models, CAD targeting defect, fault-tolerant nanoelectronic architectures.

Attaining fault tolerance while maintaining low overhead is one of the main challenges in a practical implementation of quantum circuits. One major technique that can overcome this problem is the flag technique, in which high-weight errors arising from a few faults can be detected by a few ancillas and distinguished using subsequent syndrome measurements. The technique can be further improved using the fact that for some families of codes, errors of any weight are logically equivalent if they have the same syndrome and weight parity, as previously shown in [Phys. Rev. A 104, 042410 (2021)]. In this work, we develop a notion of distinguishable fault set which captures both concepts of flags and weight parities, and extend the use of weight parities in error correction from [Phys. Rev. A 104, 042410 (2021)] to families of capped and recursive capped color codes. We also develop fault-tolerant protocols for error correction, measurement, state preparation, and logical T gate implementation via code switching, which are sufficient for performing fault-tolerant Clifford computation on a capped color code, and performing fault-tolerant universal quantum computation on a recursive capped color code. Our protocols for a capped or a recursive capped color code of any distance require only 2 ancillas, assuming that the ancillas can be reused. The concept of distinguishable fault set also leads to a generalization of the definitions of fault-tolerant gadgets proposed by Aliferis, Gottesman, and Preskill.