FIR filtering using CMOS switched-current techniques

Digital filters play a central role in modern Digital Signal Processing (DSP) systems. Finite Impulse Response (FIR) filters can provide solutions with guaranteed stability and linear phase. However, the main disadvantage of conventional FIR filter designs is that they become computationally complex, especially in applications demanding narrow transition bandwidths. Therefore, designing FIR filters with very stringent specifications and a low complexity is currently an important challenge. In this chapter, a review of the recent methods to efficiently design low-complexity linear-phase FIR filters is presented. The chapter starts with an introduction to linear-phase FIR digital filters. Then, an overview of the design methods that have been developed in literature to design low-complexity FIR filters is presented. Finally, the most common and recent of these methods along with their corresponding special structures are explained.

Digital filters play a central role in modern digital signal processing (DSP) systems. Finite impulse response (FIR) filters can provide solutions with guaranteed stability and linear phase. However, the main disadvantage of conventional FIR filter designs is that they become computationally complex, especially in applications demanding narrow transition bandwidths. Therefore, designing FIR filters with very stringent specifications and a low complexity is currently an important challenge. In this chapter, a review of the recent methods to efficiently design low-complexity linear-phase FIR filters is presented. The chapter starts with an introduction to linear-phase FIR digital filters. Then, an overview of the design methods that have been developed in literature to design low-complexity FIR filters is presented. Finally, the most common and recent of these methods along with their corresponding special structures are explained.

Chapter 2 - Design and Implementation of Digital FIR Filters

WITHDRAWN: An Optimistic Design of 16-Tap FIR Filter with Radix-4 Booth Multiplier Using Improved Booth Recoding Algorithm

PurposeTraditionally, each time a new design for a finite impulse response (FIR) filter is required, a new algorithm has to be developed specially for the FIR filter. Furthermore, corresponding hardware architecture must be designed specially to meet the requirement of the FIR specifications. The purpose of this paper is to propose an arithmetic logic unit (ALU)‐based universal FIR filter suitable for realization in field programmable gate arrays (FPGA), where various FIR filters can be implemented just by programming instructions in the ROM with identical hardware architecture.Design/methodology/approachRather than multiplier‐accumulator‐based architecture for conventional FIR, the proposed ALU architecture implements the FIR functions by using accumulators and shift‐registers controlled by the instructions of ROM. Furthermore, time division multiplexing access (TDMA) technique is employed to reduce the chip size. In addition, the proposed FIR architecture is verified in a SOC hardware and/or software co‐emulation system.FindingsAn ALU‐based universal FIR filter suitable for realization in FPGA is designed and verified in a SOC hardware/software co‐emulation system with example of a 64‐tap FIR filter design.Originality/valueA software‐based design method as well as TDMA scheme for the ALU‐based FIR filter are introduced, making FIR filter architecture universal, programmable, and consuming less FPGA resources.

Background/Objectives: FIR filters play a vital role in signal processing applications. This research work presents a low power and high speed efficient buffer based Distributed Algorithms and it is analyzed with Electro Cardio Gram (ECG) signal Finite Impulse Response (FIR) filter design. Methods/Statistical Analysis: The proposed FIR filter is designed using buffer based DA and it is simulated and synthesized using Cadence digital labs. This is compared with different architectures such as conventional DA, separated look up table DA and LUT less DA. Findings: Synthesis report shows that the proposed design has 52% less power dissipation compared with the conventional DA, 21% reduction in delay with separated Look Up Table (LUT) DA and 8% reduction in area with LUT less DA. Conclusion/Improvements: Presently this method is applied for ECG signal input with 16-tap FIR filter. This can be extended for higher order filters to achieve better performance.

An Finite Impulse Response (FIR) filter is a widely used digital filter technology whose impulse response has a finite duration. An FIR filter is usually favored for many reasons such as easy to design, easy to implement on a variety of system architectures. An FIR filter can be easily designed with a linear phase response and its output is more predictable since it doesn't have feedback components. There are both engineer and mathematical methods for designing an FIR filter so that machine learning doesn't play an important role in the FIR filter design. In this paper, we present an alternative to traditional filter design methods to direct learn the FIR filter coefficients from input data with machine learning algorithm. With the proposed algorithm, we can easily design an FIR filter from the input data mixed with designed all spectrum noise signal. To show the capability of this algorithm, an example application of suppressing background music from speech or vice versa is demonstrated in this paper. Despite that the music and speech have a lot of overlap in their spectrum, the filter designed by our algorithm can successfully suppress music or speech in a mixture of music and speech signals.

Optimisation based design of finite impulse response (FIR) filters has been an active area of research for quite some time. The various algorithms proposed for FIR filter design aim at meeting a set of desired specifications in the frequency domain. Evolutionary algorithms have been found to be very effective for FIR filter design because of the non-linear, non-differentiable and non-convex nature of the associated optimisation problem. The present work proposes two modified versions of a recently developed evolutionary technique i.e. artificial bee colony (ABC) algorithm for design of FIR filters. The applicability of the proposed approach has been evaluated by comparing its response with conventional reported filter design techniques. The proposed variants of ABC are found to outperform other non-convex algorithms in achieving the desired specifications. In addition to the simulation results, the designed filters have been implemented in hardware using Xilinx-xc7vx330t-3ffg1157 (Virtex-7) field programmable gate array. The hardware implementation allows validation of the proposed techniques for practical filtering applications by considering real time operation parameters.

SummaryThis work presents the design of an asynchronous digital finite impulse response (FIR) filter suitable for high‐performance partial response maximum likelihood (PRML) read channel ICs. A high throughput, low latency FIR filter is the basic requirement for the equalization process in read channels. To achieve the enhancement in speed and reduction in latency of the FIR filter, its computational units are deeply pipelined using high‐capacity hybrid (HC‐hybrid) logic pipeline method. The designed FIR filter has been simulated using UMC‐180 nm and UMC‐65 nm technologies. Simulation results show that the asynchronous digital FIR filter can operate up to a throughput of 1.17 Giga items/s in 180 nm and 2.3 Giga items/s in 65 nm technology yet with the latency in the order of ns.

In this communication, one novel attempt has been made towards the design of minimum-phase finite impulse response (FIR) filter using one evolutionary computation technique, named differential evolution (DE) algorithm. Mean square error (MSE) between the frequency samples of the ideal filter and the designed filter in the pass-band and stop-band region and the minimum average error (MAE) between the frequency samples in the transition-band region had been considered for the formulation of the objective function in the optimization process. Performance of the optimization technique has been monitored in terms of convergence characteristics for four different orders of FIR filter under consideration. Robustness of our proposition has been firmly established in the sense that the proposed algorithm can be suitably tuned for the design of low-pass, high-pass or band-pass FIR filter of different specifications. Supremacy of the proposed algorithm over other existing techniques for the design of minimum-phase FIR filter has been substantiated by means of frequency response and pole-zero diagrams.

In recent years, several approaches have been investigated to obtain multiplier-free realizations of digital filters. One approach makes use of periodically time-varying (PTV) structures. The idea is to distribute the computation in time and in space. Distribution in time provides reuse of the same hardware by means of PTV coefficients. Distribution in space increases the number of coefficients but simplifies the values of the coefficients. Computation distribution is based on radix-r number representation, and it can be carried out to the extent that each computation involves a simple coefficient that can be realized using only addition and shift (no hardware multiplier). Previous PTV realizations could not exploit the coefficient symmetry of finite impulse response (FIR) filters to reduce the number of coefficients. This paper proposes design and realizations of FIR filters with punctured radix-8 coefficients belonging to the septuple set {0, ±1, ±2, ±4), which can be implemented using only a shift operation without requiring any hardware multiplier. The realizations exploit the coefficient symmetry to reduce the hardware by about one-half. Due to a non-uniform grid of representation, we apply a modified Karmarkar's linear programming algorithm to find the optimum set of discrete coefficients that minimizes the weighted peak ripple error. Comparison with a conventional FIR filter with sum-of-powers-of-two (SOPOT) coefficients shows that the proposed filter is faster and uses less hardware than one with SOPOT coefficients. However, the punctured radix-8 system has a limit on the achievable ripple.

The paper presents the design and implementation of a high speed digital Finite Impulse Response (FIR) filter using unfolding transformation technique. FIR Filter has widespread applications in signal processing such as image processing, biomedical signal processing, high speed communication systems, noise elimination and many more. The speed of FIR filter can be improved with high speed vedic multiplier and with low propagation delay carry increment adder. In the proposed design, the FIR filter is unfolded by a factor 3 which results in scheduling the filter to a smaller iteration period and along with this throughput of the filter also increases. The propagation delay is reduced to almost three times in FIR filter by using faster adder, high speed multiplier and unfolding transformation technique. We have synthesized the proposed design on Xilinx ISE 14.7 with Virtex IV FPGA family. The obtained results also confirm the faster performance of the FIR filter.

In this paper we propose a novel Stochastic Computing (SC) Finite Impulse Response (FIR) filter design to improve the overall accuracy. Since SC is generated probabilistically, it incurs inherent SC process error, i.e. the larger number of SC process blocks, the larger error probability. Moreover, generation of SC from lower binary radix value produces higher percentage of error as compared to generation from higher value. In our SC FIR design, we reduce the number of SC processing blocks by reducing the number of FIR stages using fast FIR algorithm (FFA). Further we improve the inner-product performance by re-ordering the FIR filter parameters to generate higher-value SC input. Confirmed by the numerical analysis and simulation results, our novel design can implement higher-order FIR filter without reducing its output performance.

In Digital wireless communication system Finite Impulse Response (FIR) filter is used fundamentally pipelined as well as support Multiplication with Accumulation scheme (MAC) that results in important save of calculation. Efficient area along with delay recognition of great order FIR filters for update applications have been achieved by the opportunity of recognition of block FIR filter in transpose form organization. The projected transpose form block filter of update applications are developed by a general carry select adder based architecture. Secured digital FIR filter block is implemented by a pepped-up design using the MAC scheme. Booth multiplier has been used in MAC scheme. The proposed method has less area also delay than conventional filter.

Electro-hydraulic shaking tables (EHSTs) with multiple degrees-of-freedom (DOFs) are vital to large-scale structural-reliability experiments. The EHST control accuracy directly influences the qualitative and quantitative assessments of the reliability tests. Conventional three-variable control (TVC) fails to account for the coupling between the DOFs in multi-DOF EHSTs. Furthermore, TVC cannot adequately compensate for fluctuations in the acceleration frequency characteristics; thus, the waveform tracking accuracy is poor and suboptimal performance is achieved during high-precision vibration tests. An inversion feedforward control (IFC) based on the design of finite impulse response (FIR) filters is designed during this study to enhance the acceleration-waveform tracking accuracy in multi-DOF vibration tests. The iterative reweighted least squares (IRLS) algorithm is used to design the FIR filters, which are used to fit the impedance characteristics of a multi-DOF EHST. By using the designed FIR filters to filter the acceleration reference waveform, the coupling between the DOFs is compensated for, and this compensation reduces the fluctuations in the acceleration frequency characteristic and the influence of high-frequency noise. The IRLS algorithm is used to transform the passband and stopband filter design specifications into constrained least squares optimization problems. The frequency characteristics of the developed FIR filters enable high-precision fitting of both the impedance magnitude frequency and phase frequency characteristics within the bandwidth of the multi-DOF EHST system. Outside the bandwidth of the multi-DOF EHST system, the filters achieve high-decibel attenuation of the magnitude-frequency characteristic. Experimental acceleration frequency response and random waveform tracking results demonstrate that the filter-based IFC significantly enhances the random acceleration signal tracking accuracy for a multi-DOF EHST.