First Order Statistic Based Fast Blind Calibration of Time Skews for Time-Interleaved ADCs

Time-interleaved analog-to-digital converters (TI-ADCs) offer a significant increase in the available sample rate of ADCs. Their performance is degraded by timing and gain mismatches. Most of the literature on mismatch estimation and correction in TI-ADCs is concentrated on low-pass converting baseband signals. This paper provides a semi-blind solution, for both timing and gain mismatches correction, in the digital data section of a two-channel TI-ADC for band-pass input signals. This is a realistic communications system scenario. Modern system designs lean towards having the ADC interface with intermediate frequency (IF) signal in the analog section of a digital receiver rather than the DC centered, analog down converted, in-phase and quadrature pair.

A foreground digital calibration algorithm for time-interleaved ADCs with low computational complexity

This paper proposes a technique to calibrate timing mismatches in the digital domain for Time-Interleaved Analog-to-Digital Converters (TIADCs) based on second-order Taylor series approximation for application in high-speed communication and digital signal processing systems. By analyzing the error signal using second-order Taylor series approximation, the proposed technique estimates timing mismatches through the Least Mean Squares (LMS) algorithm to accelerate computation speed and reduce hardware resources. Subsequently, the timing mismatches are corrected based on the second-order Taylor series approximation. The effectiveness of the proposed technique is demonstrated through simulation results in MATLAB software. The simulation results show a significant improvement in the performance of the TIADC. Specifically, the Signal-to-Noise and Distortion Ratio (SNDR) and Spurious-Free Dynamic Range (SFDR) for a 4-channel TIADC are enhanced from 28.29 dB and 33.05 dB to 60.67 dB and 93.66 dB, respectively.

In this work, we first provide an overview of the state of the art in mismatch error estimation and correction for time-interleaved analog to digital converters (TI-ADCs). Then, we present a novel pilot-based on-line adaptive timing mismatch error estimation approach for TI-ADCs in the context of an impulse radio ultra wideband (IR-UWB) receiver with correlation-based detection. We introduce the developed method and derive the expressions for both additive white Gaussian noise (AWGN) and Rayleigh multipath fading (RMPF) channels. We also derive a lower bound on the required ADC resolution to attain a certain estimation precision. Simulations show the effectiveness of the technique when combined with an adequate compensator. We analyze the estimation error behavior as a function of signal to noise ratio (SNR) and investigate the ADC performance before and after compensation. While all mismatches combined cause the effective number of bits (ENOB) to drop to 3 bits and to 6 bits when considering only timing mismatch, estimation and correction of these errors with the proposed technique can restore a close to ideal behavior. We also show the performance loss at the receiver in terms of bit error rate (BER) and how compensation is able to significantly improve performance.

Time-Interleaved Analog-to-Digital Converter (TIADC) is a promising approach to meet the requirement of high speed wireless communication systems. However, mismatches between the channels of TIADCs generate unwanted distortions at the output spectrum. This paper demonstrates a fully digital background calibration technique to identify and compensate three all deviations which are offset, gain and timing mismatches for TIADCs. In which, offset mismatch is corrected by computing the average of the output samples of each channel. The gain and timing mismatches are compensated by using LMS algorithm and the modulation matrix m[n]. The simulation results show that the performance of the ADC is improved by 41.32 dB for SNDR and 64.6 dB for SFDR.

Digital estimation and compensation method for nonlinearity mismatches in time-interleaved analog-to-digital converters

The timing errors and especially the timing skew mismatch errors are one of the main errors that cause substantial degradation in the resolution of high-speed Time-Interleaved analog-to-digital converters (TIADCs). These errors cannot be completely corrected using blind methods such as ANC, BSS etc., because of the correlation between the desired signal and the noise as both are sampled from the same input signal. In this brief, a new algorithm using oversampling is proposed to guarantee independence between the signal and the noise. The compensation structure is a typical Adaptive Noise Cancelling (ANC) block which uses special cost function gained from the oversampling concept. To estimate the noise signal caused by the timing skew error, a new structure using modulation concept is derived from the reformulation of the timing skew error effect on the TIADC signal and oversampling assumptions. The simulation results are presented for a four-channel 10-bit TIADC in order to verify the effectiveness of the proposed method. Low computational complexity and fast convergence speed are the main advantages of the proposed algorithm.

A digital background calibration for minimising timing-error effects in time-interleaved analogue-to-digital converter (TIADC) is presented. A technique for correcting sampling time error in a four-channel TIADC system is described. Simulation results show that the proposed calibration technique can significantly improve the SFDR performance for the 12-bit TIADC system.

A software-defined radio (SDR) for ultrawideband (UWB) communication systems places several stringent requirements on the analog-to-digital converter (ADC). One alternative to using a single ADC is to sample the received signal with an array of lower speed ADCs that were driven by interleaved sampling clocks; however, mismatches among the ADCs will result in signal distortion. This paper makes three important contributions to overcoming this problem: 1) analytical quantification of the impact of ADC gain, offset, and timing mismatches on the performance of a time-interleaved sampling ADC array for UWB signals; 2) demonstration of the efficacy of using a pilot-based matched-filter architecture to mitigate the impact of timing mismatches in the presence of multipath; and 3) implementation of an 8-ADC time-interleaved UWB SDR testbed that operates at an effective sampling frequency of 6.4 GHz. In addition, our findings allow for the design specification of the number of pilots required to obtain a desired system performance. The simulation and measured performance results from this paper demonstrate that ADC mismatches can be controlled to within plusmn10%, yielding acceptable levels of distortion and bit-error-rate (BER) performance on the UWB SDR testbed. Both analytical and simulation results also demonstrate the efficacy of a pilot-based matched filter in mitigating the impact of timing mismatch errors, even in the presence of multipath.

This paper describes a digital calibration method for reducing the distortion created by timing mismatch in a four-channel time-interleaved analog-to-digital converter (TIADC). It bases on a coordinate rotation digital computer (CORDIC) algorithm for estimating the timing error and a multistage differentiator-multiplier cascade structure for timing error correction. Frequency of the testing signal using for estimation almost ranges from zero to Nyquist frequency of the system. For correction method, the differentiators are implemented with fixed filter coefficients and only several multipliers need to be adapted during operation such that implementation costs are reduced. Moreover, numerical simulations show a rather high performance for both estimation and correction.

We introduce a novel randomization method for time-interleaved analog-to-digital converters (TIADCs). In contrast to conventional randomization methods our method improves the signal-to-noise and distortion ratio (SINAD) and the spurious free dynamic range (SFDR) by combining randomization of channel ADCs and spectral shaping of timing mismatches. The new method can exploit information about timing mismatches of the channel ADCs in order to optimize the randomized sequence. We provide the theoretical background, discuss aspects of the advanced randomization, and present simulation results

Today's applications such as broadband satellite receivers, cable TVs, and software-defined radios require highly efficient ADCs with high sampling rates and high resolutions. A time-interleaved ADC (TIADC) is a popular architecture used to achieve this goal. However, this structure suffers from mismatches between the sub-converters, which cause errors on the output signal, and more significantly, decrease the SFDR. These mismatches can be a severe limitation in applications such as satellite reception, where both narrowband and wideband signals are used. This paper introduces digital derivative-based estimation of timing mismatches. Gain, offset and skew mismatch calibrations are performed entirely in the digital domain through equalization.

This paper presents a method for all-digital background calibration of multiple channel mismatches including offset, gain and timing mismatches in time-interleaved analog to digital converters (TIADCs). The averaging technique is used to remove the offset mismatch at each channel. The gain mismatch is calibrated by calculating the power ratio of the subADC over the reference ADC. Timing skew is compensated by using Hadamard transform for error correction and least mean squares (LMS) algorithm for estimation of the clock skew. The performance improvement of TIADCs employing these techniques is demonstrated through numerical simulations.

We present a novel method for the estimation and correction of mismatch errors in time-interleaved analog-to-digital converters. The estimation of the mismatch errors requires a training signal, but it is efficient, accurate, and effective while keeping low the complexity of the associated algorithm, when compared with other works in the literature. The compensation strategy uses the estimated parameters for offset and gain mismatch error correction, and implements a low-complexity (similar to that of a finite-impulse response filter) Lagrange interpolation filter to correct errors due to timing mismatch, which depends on the dynamics of the input signal. The proposed compensation strategy achieves almost ideal behavior over a wide bandwidth, i.e., only 12% of oversampling is required for an almost complete cancelation of distortion. The method has been tested under severe mismatch conditions (up to 10% timing mismatch and 5% gain and offset mismatch), showing an improvement of over 6 bits in the effective number of bits and 50 dB in the spurious-free dynamic range. In addition, when compared with the available techniques, no limitation on the number of channel converters is introduced since the compensator effectively cancels the distortion even in the presence of large mismatches.

Offset, gain and time mismatch errors exist in the channels of the time-interleaved analog-to-digital converter (TIADC), which severely affect the signal-to-noise and distortion ratio (SNDR), spurious-free dynamic range (SFDR) and effective number of bits (ENOB). Here, an error detection and correction method of TIADC based on genetic algorithm (GA) optimization is presented. The algorithm based on sine fitting is used for the first estimation and rough correction of the input signal, and GA is used for the second detection and fine correction of channel mismatch errors on the signal after frequency domain filtering. Experimental results show that the SNDR of the TIADC system is enhanced to 92.24 dB, the SFDR is enhanced to 102.05 dB, the ENOB is enhanced to 15.03 bits and the spectrum spurs are reduced. This method provides a new idea for error detection and correction of high-resolution TIADC systems with more than 16 bits.