Flexible Switching Architecture with Virtual-Queue for Time-Sensitive Networking Switches

Quality of service provision in combined input and crosspoint queued switches without output queueing match

Output queuing is well known for its ability to provide Quality-of-Service (QoS) guarantees. Unfortunately, the high-speed memory requirements of output queued (OQ) switch limit its use for large capacity switching architecture. A lot of work in literature has investigated how to emulate OQ switch with other switch architectures. A novel approach is constructing switches with buffered crossbars. However, most of the presented schemes still need a mild speedup which will incur significant cost for high speed network application. This paper investigates how to build a buffered crossbar switch to emulate OQ switch with no speedup. We first present a 2-dimensional buffered crossbar as a switch fabric and prove that a combined input-crosspoint-output queued (CICOQ) switch with such a fabric can emulate a restrict PIFO-OQ switch with no speedup. Then, we present a pretreatment mechanism used in scheduling input queues. With such a pretreatment mechanism, the CICOQ switch is proved to be able to emulate a general PIFO-OQ switch with no speedup. All scheduling algorithms used in proving OQ emulation are distributed, hence are practical.

Feature Issue on Next-Generation WDM Network Design and Routing (WDMN). We present a new architecture of an optical burst-switching (OBS) switch that consists of several buffered stages using wavelength-division multiplexing (WDM) fiber delay lines for buffering. The proposed switch architecture can cost effectively implement a large buffer depth. The use of WDM in sharing the fiber delay lines allows the proposed switch to emulate efficiently an output buffered switch using random-access memory under first-in first-out (FIFO) scheduling. To handle the case of non-FIFO scheduling, such as fair queueing, the buffered stages are interconnected by a switching fabric so that intermediate increment of burst delays is possible and non-FIFO scheduling algorithms can be implemented. Thus the proposed switch can deal with bursty traffic and provide different quality of service (QoS). Simulations have been performed to verify the performance of the proposed switch architecture for providing differentiated services (DiffServ). The proposed switch architecture is also compared with other switch architectures in the literature.

General models for a class of nonblocking architectures of asynchronous transfer mode (ATM) switches are described. Hardware aspects are discussed to show the implementation feasibility of the proposed switch architectures by means of the current technology. Performance issues are studied to point out the traffic bottlenecks of the different structures. It is shown that the classification of queueing is the main concept that enables the classification of nonblocking ATM switches. Three main packet queueing strategies can be adopted in the switching fabric: input queueing, shared queueing, and output queueing. Switch architectures adopting only one of these strategies are described. The ways in which two strategies can be jointly adopted in a switching fabric to result in the mixed queueing strategies input-output queueing, input-shared queueing, and shared-output queueing are also discussed. >

IEEE 802.1 Time-Sensitive Networking (TSN) assures a guaranteed data delivery with limited latency, low jitter, and amazingly low loss of data in handling time-critical traffic. TSN handles different quality of service (QoS) requirements and frame preemption is one of the key features of TSN. In the healthcare sector networking technology preferred by large organizations uses an enormous number of nodes, and thereby, the complexity of the network increases. Since the priority of the medical data varies at times based on the patient's health, dynamic traffic scheduling mechanisms are preferred. To improve the efficiency of the network, the software-defined access mechanism is used to control the network switches and bridges in the time-sensitive network. This work uses reinforcement learning to identify and eliminate the bridges dropping packets, and the alternative path is used to schedule the real-time data traffic. It is perceived that it performs well for the time-critical data in congestion network, increases the throughput, and reduces latency.

With the interconnection of distributed devices from different industrial automation networks, heterogeneous traffics with different Quality of Service (QoS) requirements increase dramatically. Shapers in Time-Sensitive Networking (TSN) enable the coexistence of different industrial traffics within a single network infrastructure. In this paper, with full consideration of the time-criticality of different industrial traffics and shaping mechanisms, we propose a network calculus-based modeling scheme for the widely-used Credit Based Shaper (CBS) and Time Aware Shaper (TAS). Then, we analyze the QoS of industrial traffics with different real-time characteristics by CBS and TAS, respectively. To evaluate the accuracy of network calculus-based modeling scheme, we compare our theoretical analysis with simulations, wherein a compactness function is defined to describe QoS compactness. Simulation results verify the effectiveness of proposed modeling scheme, by which we further validate both CBS and TAS can satisfy the QoS of traffics for different industrial automation scenarios.

ATM is based on the efforts of the ITU-T Broadband Integrated Services Digital Network (B-ISDN) standard. It was originally conceived as a high-speed transfer technology for voice, video, and data over public networks. The ATM Forum has broadened the ITU-T's vision of ATM for extended use over public and private networks, multi-protocol support and mobile ATM. There are also some ATM applications in High Performance Computing (HPC). ATM is a packet switching technique based on a virtual circuit mechanism. Data flows are statistically multiplexed and communication resources are dynamically shared. Therefore the high performance ATM switch is essential for quality of services (QoS). This thesis introduces typical ATM switch architecture design and analyses design problems. The research objective is to propose a switch architecture design that can solve or improve those existing problems to achieve a superior performance. The research goal is an integrated ATM switch architecture that will handle both unicast and multicast packets. Unlike the usual design for the multicast ATM switch which concentrates on a cell copy network with a unicast switching network, the proposed switch architecture processes the network packets in a single switching block, and allows unicast and multicast packets to co-exist without competing. The switch design has a simple topology and operation principle and is easy to implement. Furthermore, no copy network is required. Three major components are proposed to form the core of the new switch architecture: the parallel buffering strategy for improved buffer performance, the fast table lookup algorithm for packet duplication and routing, and the relay ring controller for solving the contention problem associated with multiple packets destined for the same output port. A mathematical model is presented and its numerical results are analysed. In addition, the simulation algorithms for the proposed switching design are presented and compared against the switching design with input and output buffering strategies. The simulation results are also compared and analysed against the numerical results. A multicast traffic model is also presented. Its performance calculation for the proposed switch is achieved through simulation. Performance analysis is compared against the output buffering switch under the same multicast traffic model. The performance analysis shows that the proposed switch architecture achieves high throughput with low cell loss rate and low time delay. Its performance can be as good as the output buffering strategy or better. Therefore the proposed switch design has solved the problems associated with input and output buffering. This thesis also analyses the complexity of the proposed switch architecture and suggests a topology to build a large scale ATM switch. The suitability and feasibility for production implementation are also addressed.

Defending against fake VIP in scant-transparency information systems with QoS differentiation

Growing demand for differentiated services and the proliferation of Internet multimedia applications requires not only faster switches/routers, but also the inclusion of guaranteed qualities of service (QoSs) and support for multicast traffic. Here, the authors introduce a parallel shared memory (PSM) architecture that addresses these demands by offering both QoS guarantees and support for multicast traffic. It is well known that PSM architectures represent an effective approach for distributing the high-memory bandwidth requirement found in output-queued (OQ) switches, while maintaining their desirable performance attributes. At the core of the PSM architecture is a memory management algorithm that determines, for each arriving packet, the memory unit in which it will be placed. The PSM architecture discussed should be considered with the context of fabric on a chip in mind, where an implementation is conceivable on a single chip, providing a plug-in emulated OQ switching solution. A description and detailed analysis of an efficient memory management algorithm that supports QoS and multicast traffic is given with a discussion of hardware implementation considerations that highlight the PSM architecture's scalability and performance attributes.

To provide Quality of Service (QoS) and data rate differentiation, we investigate in this paper a 2 dimensional optical code division multiple access (OCDMA) technique. A 2D multi-weight coding scheme with parallel mapping technique is developed. The system enhancement is assessed thanks to the use of Forward Error Correction (FEC) based on Low Density Parity Check (LDPC) codes. In order to have an efficient correction power, we develop an adaptation of the LDPC decoding algorithm to the specific multiple access interference distribution in a multimedia OCDMA network. The proposed network permits a high number of users to communicate with high data rates adapted to a multimedia transmission (voice, data and video) with corresponding QoS (10-3, 10-6, 10-9).

The software is created and constructed to address particular issues in the applied field. In this context, there is a need to be aware of the crucial characteristics to assess the quality of software. But not all software requires checking all the quality-of-service parameters, resulting in effort loss and time consumption. Therefore, it is required to develop software quality characteristics recommendation model to address and resolve the issue. The proposed work involved in this paper can be subdivided into three main parts (1) a review of popular software quality models and their comparison to create a complete set of predictable, and (2) the design of an ML-based recommendation model for recommending the software quality model and software quality characteristics (3) performance analysis. The proposed recommendation system utilizes the different software quality of service attributes as well as the software attributes where these models are suitably applied to satisfy the demands. Profiling of applications and their essential requirements have been performed Based on the different quality of service parameters and the requirements of applications. These profiles are learned by machine learning algorithms for distinguishing the application-based requirement and recommending the essential attributes. The implementation of the proposed technique has been done using Python technology. The simulation aims to demonstrate how to minimize the cost of software testing and improve time and accuracy by utilizing the appropriate quality matrix. Finally, a conclusion has been drawn and the future extension of the proposed model has been reported.

The buffered crossbar switch architecture has recently gained considerable research attention. In such a switch, besides normal input and output queues, a small buffer is associated with each crosspoint. Due to the introduction of crossbar buffers, output and input contention is eliminated, and the scheduling process is greatly simplified. We analyze the performance of switch policies by means of competitive analysis, where a uniform guarantee is provided for all traffic patterns. The goal of the switch policy is to maximize the weighted throughput of the switch, that is the total value of packets sent out of the switch. For the case of unit value packets (Best Effort), we present a simple greedy switch policy that is 4-competitive. For the case of variable value packets, we consider the Priority Queueing (PQ) mechanism, which provides better Quality of Service (QoS) guarantees by decreasing the delay of real-time traffic. We propose a preemptive greedy switch policy that achieves a competitve ratio of 18. Our results hold for any value of the switch fabric speedup. Moreover, the presented policies incur low overhead and are amenable to efficient hardware implementation at wire speed. To the best of our knowledge, this is the first work on competitive analysis for the buffered crossbar switch architecture.

There is a widespread interest in switching architectures that can scale in capacity with increasing interface transmission rates and higher port counts. Furthermore, packet switches that provide Quality of Service (QoS), such as bandwidth and delay guarantees, to the served user traffic are also highly desired. This report addresses the issue of constructing a high-capacity QoS-capable, multi-module switching node. Output queued switches provide the best performance in terms of throughput as well as QoS but do not scale. Input queued switches, on the other hand, require complex arbitration procedures to achieve the same level of performance. We enumerate the design constraints in the construction of a packet switch and present several approaches to build a system composed of lower-capacity memory and space elements, and analyze their performance. Towards this goal, we establish a new taxonomy for a class of switches, which we call Buffered Clos switches, and present a formal framework for optimal packet switching performance, in terms of both throughput and QoS. Within the taxonomy, we augment the existing combined input-output queueing (CIOQ) systems with Aggregation and Pipelining techniques. Furthermore, we present the design and analysis of a novel parallel packet switch architecture. For the items in the taxonomy, we present algorithms that provide optimal throughput and QoS, in accordance with the above performance framework. While some of the presented ideas are still in the investigative stage, we believe that the current state of the work, especially the formal treatment of switching, will be beneficial to the ongoing research in the field.

Approximate Markov chains for the performance of banyan networks built with basic switches of arbitrary size containing input queues, output queues or a combination of input buffers and output queues are presented. These chains are also extended to model banyans where each link is replaced by a number of parallel links. Comparison with simulations indicates that the chains are reasonably accurate for practical network loads. It is shown that banyans built with switches containing a combination of single input buffers and output queues outperforms banyans built with switches containing only input queues or only output queues. Banyans built with larger nodes are shown to outperform banyans built with smaller nodes. It is shown that banyan-based networks with multiple links can be designed to have extremely low blocking probabilities. >

Output Queuing (OQ) and Input Queuing (IQ) are the two basic queuing strategies implemented in routers. IQ has been identified as the simplest and the most scalable. However, the IQ only achieves 58.6% throughput due to the Head Of Line (HOL) blocking effect. The Virtual Output Queuing (VOQ) strategy is a proffered solution to the HOL blocking. It has been shown that VOQ can achieve a 100% throughput with an effective scheduling algorithm. This paper proposes a Multi stage Queuing and Scheduling architecture in which VOQ is implemented at the input and OQ at the output. The scheduling algorithm for the VOQ presented in this paper is an Iterative Probabilistic Scheduling.