FlexRAM: Toward an advanced Intelligent Memory system

Programming by questionnaire combines aspects of decision table programming and general purpose programming by using decision tables to construct an application program through the selection of certain source statements from a predefined file. It is proposed that programming by questionnaire is a useful compromise between general and special purpose programming for a significant class of large scale problems. The elements of the approach are discussed and an existing application is described.

With the capability of completing a task or achieving a goal in an uncertain environment while simultaneously having the characteristics of adaptability, self‐optimization, self‐diagnostics, and self‐maintenance, intelligent systems have witnessed extraordinary progress in recent years. These advances involve robotics, artificial intelligence and machine learning, automation, human–machine interfaces, the Internet of Things, control theory and control systems, smart and responsive materials, intelligent sensing systems, and programmed self‐assembly. As an active technology conveying mechanical stimuli to a wide range of electrical and optical signals, tactile sensors are essential elements of intelligent systems and have accelerated the emergence of advanced intelligent systems by enabling the accurate recognition and safe interaction of humans and machines, smart sensing of control systems, precise control of robotics, and synergetic work of artificial intelligent systems. Herein, the recent advances of tactile sensors for advanced intelligent systems are reviewed, emphasizing these with the working principles of piezoresistance, resistance, capacitance, piezoelectricity, triboelectricity, and optics. Representative examples of their applications in advanced intelligent systems, such as robotics, human–machine interfaces, and artificial intelligence, are explored. The remaining challenges and perspectives in this emerging field are also discussed.

The memory system is a fundamental performance and energy bottleneck in almost all computing systems. Recent system design, application, and technology trends that require more capacity, bandwidth, efficiency, and predictability out of the memory system make it an even more important system bottleneck [36, 38]. At the same time, DRAM and flash technologies are experiencing difficult technology scaling challenges that make the maintenance and enhancement of their capacity, energy efficiency, and reliability significantly more costly with conventional techniques (see, for example [13, 17--19, 23, 25, 26, 29, 30, 40]). In fact, recent reliability issues with DRAM, such as the RowHammer problem [23], are already threatening system security, predictability and robustness.

This paper presents a helper thread prefetching scheme that is designed to work on loosely-coupled processors, such as in a standard chip multiprocessor (CMP) system or an intelligent memory system. Loosely-coupled processors have an advantage in that fine-grain resources, such as processor and L1 cache resources, are not contended by the application and helper threads, hence preserving the speed of the application. However, inter-processor communication is expensive in such a system. We present techniques to alleviate this. Our approach exploits large loop-based code regions and is based on a new synchronization mechanism between the application and helper threads. This mechanism precisely controls how far ahead the execution of the helper thread can be with respect to the application thread. We found that this is important in ensuring prefetching timeliness and avoiding cache pollution. To demonstrate that prefetching in a loosely-coupled system can be done effectively, we evaluate our prefetching in a standard, unmodified CMP system, and in an intelligent memory system where a simple processor in memory executes the helper thread. Evaluating our scheme with nine memory-intensive applications with the memory processor in DRAM achieves an average speedup of 1.25. Moreover, our scheme works well in combination with a conventional processor-side sequential L1 prefetcher, resulting in an average speedup of 1.31. In a standard CMP, the scheme achieves an average speedup of 1.33.

Deep Neural Networks (DNNs) are often associated with a large number of data-parallel computations. Therefore, data-centric computing paradigms, such as Processing in Memory (PIM), are being widely explored for DNN acceleration applications. A recent PIM architecture, developed and commercialized by the UPMEM company, has demonstrated impressive performance boost over traditional CPU-based systems for a wide range of data-parallel applications. However, the application domain of DNN acceleration is yet to be explored on this PIM platform. In this work, we present successful implementations of DNNs on the UPMEM PIM system. We explore multiple operation mapping schemes with different optimization goals and accelerate two CNN algorithms using these schemes. Based on the data achieved from the physical implementation of the DNNs on the UPMEM system, we compare the performance of our DNN implementation with several other recently proposed PIM architecture.

With the rapid development of medical imaging technology and computer technology, the medical imaging artificial intelligence of computer-aided diagnosis based on machine learning has become an important part of modern medical diagnosis. With the application of medical image security technology, people realize that the difficulty of its development is the inherent defect of advanced image processing technology. This paper introduces the background of colorectal cancer diagnosis and monitoring, and then carries out academic research on the medical imaging artificial intelligence of colorectal cancer diagnosis and monitoring and machine learning, and finally summarizes it with the advanced computational intelligence system for the application of safe medical imaging.In the experimental part, this paper wants to carry out the staging preparation stage. It was concluded that the staging preparation stage of group Y was higher than that of group X and the difference was statistically significant. Then the overall accuracy rate of multimodal medical image fusion was 69.5% through pathological staging comparison. Finally, the diagnostic rate, the number of patients with effective treatment and satisfaction were analyzed. Finally, the average diagnostic rate of the new diagnosis method was 8.75% higher than that of the traditional diagnosis method. With the development of computer science and technology, the application field was expanding constantly. Computer aided diagnosis technology combining computer and medical images has become a research hotspot.

Adaptive multivariate regression for advanced memory system evaluation: application and experience

On the 16th of June the ACM SIGPLAN Workshop on Memory System Performance (MSP'02) was held in Berlin, Germany. MSP'02 is a new workshop that focuses on software techniques to address the memory wall.Given current technology trends that forecast a rapidly growing processor-memory speed imbalance, optimizing a program's memory system performance has become increasingly important. Much research has focused on improving the cache performance of scientific programs that use arrays as their primary data structure. Unfortunately, these techniques are not a complete solution for general purpose programs, which manipulate more complex and dynamic data structures. While recent research has begun to address this problem, much work remains to be done.The focus of this workshop is on all aspects of improving the memory system performance of general-purpose programs. This includes novel techniques for profiling memory system behavior, new analyses (both static and dynamic) for identifying and understanding memory-related performance problems, and finally optimizations for improving memory system performance. Software, hardware as well as hybrid approaches are encouraged. In addition, studies of application that describe problems and experience with memory performance related issues in specific application domains are of interest. The objective of the workshop is to bring together programming language researchers in the areas of program analysis and compiler optimization, computer architects, operating system researchers, and application programmers. We hope that this will be the first in a series of workshops that will encourage collaboration across these fields while at the same time expand program optimization research towards an area of great practical importance.MSP'02 features an invited talk and presentations of ten refereed papers. The papers were selected out of fifteen submissions. Fifteen PC members and additional external reviewers prepared multiple written reviews for each submission. The recommendations of the referees determined an initial set of papers selected for acceptance. The members of the program committee were then given the option to resolve differences in opinion for the papers they refereed based on the written reviews during the program committee tele-conferenee meeting. After the resolution process, the 10 papers included in the workshop proceedings were selected for presentation and publication.

The Deep Neural Network (DNN), Recurrent Neural Network (RNN) applications, rapidly becoming attractive to the market, process a large amount of low-locality data; thus, the memory bandwidth limits their peak performance. Therefore, many data centers actively adapt high-bandwidth memory like HBM2/HBM2E to resolve the problem. However, this approach would not provide a complete solution since it still transfers the data from the memory to the computing unit. Thus, processing-in-memory (PIM), which performs the computation inside memory, has attracted attention. However, most previous methods require the modification or the extension of core pipelines and memory system components like memory controllers, making the practical implementation of PIM very challenging and expensive in development. In this article, we propose a Silent-PIM that performs the PIM computation with standard DRAM memory requests; thus, requiring no hardware modifications and allowing the PIM memory device to perform the computation while servicing non-PIM applications' memory requests. We can achieve our design goal by preserving the standard memory request behaviors and satisfying the DRAM standard timing requirements. In addition, using standard memory requests makes it possible to use DMA as a PIM's offloading engine, resulting in processing the PIM memory requests fast and making a core perform other tasks. We compared the performance of three Long Short-Term Memory models (LSTM) kernels on real platforms, such as the Silent-PIM modeled on the FPGA, GPU, and CPU. For (p ×512) ×(512 ×2048) matrix multiplication with a batch size p varying from 1 to 128, the Silent-PIM performed up to 16.9x and 24.6x faster than GPU and CPU, respectively, p=1, which was the case without having any data reuse. At p=128, the highest data reuse case, the GPU performance was the highest, but the PIM performance was still higher than the CPU execution. Similarly, at (p ×2048) element-wise multiplication and addition, where there was no data reuse, the Silent-PIM always achieved higher than both CPU and GPU. It also showed that when the PIM's EDP performance was superior to the others in all the cases having no data reuse.

The Engineering discipline has relied on computers to perform numerical calculations in many of its sub-disciplines over the last decades. The advent of graphical processing units (GPUs), parallel stream processors, has the potential to speed up generic simulations that facilitate engineering applications aside from traditional computer graphics applications, using GPGPU (general purpose programming on the GPU). The potential benefits of exploiting the GPU for general purpose computation require the program to be highly arithmetic intensive and also data independent. This paper looks at the specific application of the Conjugate Gradient method used in hydraulic network solvers on the GPU and compares the results to conventional central processing unit (CPU) implementations. The results indicate that the GPU becomes more efficient as the data set size increases. However, with the current hardware and the implementation of the Conjugate Gradient algorithm, the application of stream processing to hydraulic network solvers is only faster and more efficient for exceptionally large water distribution models, which are seldom found in practice.

I start with a brief introduction to the graphics processing unit (GPU) as well as general-purpose computation on modern graphics hardware (GPGPU). Next, I explore the motivations for GPGPU programming, and the capabilities of modern GPUs (including advantages and disadvantages). Also, I give the background required for further exploring GPU programming, including the terminology used and the resources available. Finally, I include a comprehensive survey of previous and current GPGPU work, and end with a look at the future of GPU programming.

Many modern workloads, such as neural networks, databases, and graph processing, are fundamentally memory-bound. For such workloads, the data movement between main memory and CPU cores imposes a significant overhead in terms of both latency and energy. A major reason is that this communication happens through a narrow bus with high latency and limited bandwidth, and the low data reuse in memory-bound workloads is insufficient to amortize the cost of main memory access. Fundamentally addressing this data movement bottleneck requires a paradigm where the memory system assumes an active role in computing by integrating processing capabilities. This paradigm is known as processing-in-memory (PIM). Recent research explores different forms of PIM architectures, motivated by the emergence of new 3D-stacked memory technologies that integrate memory with a logic layer where processing elements can be easily placed. Past works evaluate these architectures in simulation or, at best, with simplified hardware prototypes. In contrast, the UPMEM company has designed and manufactured the first publicly-available real-world PIM architecture. The UPMEM PIM architecture combines traditional DRAM memory arrays with general-purpose in- order cores, called DRAM Processing Units (DPUs), integrated in the same chip. This paper provides the first comprehensive analysis of the first publicly-available real-world PIM architecture. We make two key contributions. First, we conduct an experimental characterization of the UPMEM-based PIM system using microbenchmarks to assess various architecture limits such as compute throughput and memory bandwidth, yielding new insights. Second, we present PrIM (Processing-In-Memory benchmarks), a benchmark suite of 16 workloads from different application domains (e.g., dense/sparse linear algebra, databases, data analytics, graph processing, neural networks, bioinformatics, image processing), which we identify as memory-bound. We evaluate the performance and ...

Processing-in-memory (PIM) architectures cannot use traditional approaches to cache coherence due to the high off-chip traffic consumed by coherence messages. We propose LazyPIM , a new hardware cache coherence mechanism designed specifically for PIM. LazyPIM uses a combination of speculative cache coherence and compressed coherence signatures to greatly reduce the overhead of keeping PIM coherent with the processor. We find that LazyPIM improves average performance across a range of PIM applications by 49.1 percent over the best prior approach, coming within 5.5 percent of an ideal PIM mechanism.

The book at hand constitutes the inaugural volume in the new Springer series on Learning and Analytics in Intelligent Systems. The series aims at making available a publication of books in hardcopy and soft-copy form on all aspects of learning, analytics and advanced intelligent systems and related technologies. These disciplines are strongly related and complement one another significantly. Thus, the new series encourages a unified/integrated approach to themes and topics in these disciplines which will result in significant cross-fertilization, research advancement and new knowledge creation. To maximize dissemination of research results and knowledge, the series will publish edited books, monographs, handbooks, textbooks and conference proceedings. The book at hand is directed towards professors, researchers, scientists, engineers and students. An extensive list of references at the end of each chapter guides readers to probe further into application areas of interest to them.

The 8th International Symposium on Advanced Intelligent Systems (ISIS 2007), a biennial joint conference between Korea and Japan, focuses on artificial intelligence, intelligent systems, information technology, and their applications. ISIS 2007, held on September 5-8 at Soraksan National Park under the auspices of the Korea Fuzzy Logic and Intelligent Systems Society (KFIS), was attended by 265 researchers, engineers, and other professionals and featured 206 presentations. Of more than 20 papers preliminarily selected and reviewed by the ISIS 2007 International Program Committees, 7 were chosen for the special issue of the Journal of Advanced Computational Intelligence and Intelligent Informatics, centering on advanced intelligent systems including robotics, pattern recognition, data mining, and decision-making systems. The content and conclusions presented in these fine papers should prove both interesting and informative to specialists and generalists alike. I thank the authors and reviewers for their painstaking contributions to this special issue and Prof. Kaoru Hirota of the Tokyo Institute of Technology for inviting me to guest-edit this work.