Flip-Chip Technologies, Applications, Market Status and Forecasts

The demand for portable, multi-functional and compact electronic products raises a great challenge to the substrate technology and related interconnection technology in electronic packaging for high density, small feature size and high performance. The requirement on the circuit density of substrate, especially, is intensive for chip scale packages (CSP) and system-in-package (SIP), where the chip size is reduced and its pin-count number is increased. Thus, the formation of small and dense via is becoming more and more important for increasing the circuit density of substrate. In this paper, ultra-fine blind via with solid Cu filled at an entry diameter of 20 mum, over the current blind via size of 50-200 mum by CO2 laser drilling, is demonstrated on polyimide based flexible substrate. Its advantages of the present innovation compared to the PTH in conventional substrate technology and micro-blind via structure in advanced high density interconnect (HDI) technology will be explored. In conclusions, the reliability of the ultra-fine blind vias has been assessed in 2-metal tape ball grid array (TBGA) and daisy chain modules at substrate level, subjected to JEDEC MST L3 at 260degC, Air to Air thermal cycle and thermal shock, T/H bias, pressure cooker test and low/high temperature storage tests, etc. In addition, the Cu fully filled ultra-fine blind via makes landless structure feasible on the substrate, further increasing the circuit density of substrate. In the end, the ultra-fine Cu filled blind via technology has introduced to the production in Compass for SIP, 2-metal layer chip-on-flex (COF) and multi-layer buildup flex, etc.

As the data rate of high performance Internet router systems continues to increase, meeting the challenges for high speed electrical performance drives ASIC packaging technology to higher silicon integration, higher I/O density, and enhanced thermal power dissipation. The requirement of high Si integration with the increasing needs for embedded SRAM and DRAM drives for the increase in Si die size and the demand for 90nm technology. Die size up to 20/spl times/20 mm is pushing advanced packaging substrate technology. High I/O density also drives the needs for finer bump pitch and larger package body size, which present challenges for package and card level assembly. Moreover, high availability telecommunication products demand excellent reliability not only at the ASIC package and card assembly level, but also at the final product system level.

Due to the increasing demand for higher performance, greater flexibility, smaller size, and lighter weight in mobile electronic products, there have been growing needs of wearable electronic products in near future. Wearable watches, glasses, wrist bands, shoes, and clothes have been recently introduced in the market. In order to realize flexible wearable electronics, flexible components have to be packaged and interconnected with flexibility using flexible packaging technologies. As a one of the promising flexible packaging and interconnection technologies using flexible substrates such as polymer films and fabrics, fabrics can provide great flexibility and durability. Therefore, fabric-based fine pitch interconnection using ACFs materials will provide the solution for realizing various flexible wearable electronic products. In the electronic packaging technology for fabric-based wearable electronics, FOF(Flex On Fabric) technologies using FPCs substrates and various fabrics with fine pitch circuits using ACFs interconnection materials become very important, because ACF interconnection provides excellent electrical flexibility compared with conventional solder-or socket-based interconnection methods which have a limitation of bending and flexing.

Packaging technologies such as fan out wafer level packaging (FOWLP) and embedded chip in substrate technologies have gained a lot of attention recently from OEMs, OSATS, technology developers, and technology integrators in the integrated circuit (IC) industry as schemes for continuing wafer level chip scale package (WLCSP). Both technologies are focused on incorporating ICs into their packaging platform and on taking advantage of current process recipes and infrastructure as much as possible. However, by virtue of the new process steps and technologies required to get to 3-D packaged materials, such as through silicon vias (TSVs), wafer thinning and handling processes and requirements for alternative dielectric materials, many opportunities have arisen. Expectations are that many devices that follow a flip chip ball grid array (FCBGA) flow or WLCSP will adopt an embedded technology strategy for future generations. FOWLP has several advantages, over FCBGA and WLCSP including potential for system in package (SIP) configurations and 3-D integration, the ability to overcome pad limitation issues, and shorter interconnections and so higher electrical performance. However, to gain these advantages, requirements for processing will change due to the significant demands imposed on the materials used as permanent dielectric layers and the photoresists used in the fabrication processes. Cleaning chemistry must be designed to remove challenging films such as photoresists and residues created during other process steps; yet preserve the exposed metals such as the bond pads and Cu redistribution lines, as well as the permanent dielectrics. Device reliability and performance is heavily dependent on the proper working of all these components. The focus of this paper is to identify a manufacturable and reliable process and process window for removal of positive photoresists and residues in formation of under bump metallization (UBM) and contact pads in wafer level packaging (WLP). Our objective is to discuss a proven process that has been successfully implemented into a manufacturing environment. It has improved robustness and reliability over past-used solutions due to decreased sensitivity to moisture contamination, a significant cause of defects in many device applications.

Due to the increasing demand for higher performance, greater flexibility, smaller size, and lighter weight in mobile and wearable electronic products, there have been growing needs of various electronic packaging products and fine-pitch interconnection technologies. To realize various state-of-art mobile and wearable electronic products, fine pitch and flexible packaging & interconnection technologies are needed. As one of the promising fine pitch and flexible packaging and interconnection technologies, conductive adhesive films materials such as ACFs(Anisotropic Conductive Films) and NCFs(Non Conductive Films) are widely used now. In general, ACFs have two technical limitations such as (1) ultra-fine pitch shortage free interconnection and (2) higher current handling capability. For (1) ultra-fine pitch applications without electrical shortage, new concept of Nano-fiber ACFs and APL(Anchoring Polymer Layer) ACFs have been successfully invented by KAIST both for less than 20 micron pitch COG(Chip On Glass), COP(Chip On Polymer). and COF(Chip On Flex). And they can be also used for less than 50 micron pitch FOF(Flex On Flex) and FOB(Flex On Board) applications. In addition, for (2) higher current handling capability applications, new solder ACFs have been also introduced by KAIST to replace the conventional metal particles based ACFs interconnection. By solder ACFs, 30% low contact resistance, 4 X higher current handling capability, and excellent reliability were successfully achieved compared with conventional ACFs. Furthermore, ACFs materials-based packaging and interconnection method can provide the flexible interconnect solution for OLED(Organic LED) COP and COF/CIF(Chip In Flex) packages to realize wearable electronic products.Recently the 3-D die chip stacking using the Through silicon via (TSV) technology has been widely used for stacking memory and ASIC chips. In the 3D-TSV vertical interconnection, Cu pillar/Sn-Ag eutectic solder bump is one of the promising bonding method. After the 3D-TSV chips are interconnected with the bumps, the gap between stacked chips should be filled with underfill materials. However, capillary flow underfill between 3D-TSV stacked chips become difficult because of increased chip/wafer area, decreased gap height, and multiple chip/wafer stacking. Therefore, new bonding method using NCFs materials, which performs both Cu-pillar/Sn-Ag flip chip bump to metal pads interconnection and underfils at the same time has been extensively used.In this presentation, the ACFs materials for ultra-fine pitch and higher current carrying interconnection and the NCFs for 3D-TSV chip stacking applications will be introduced.

Motorola's Interconnect Systems Laboratory in Munich has developed the assembly technology for a mechatronic multichip power module, a new intelligent connector for automotive applications. Product's requirements for simultaneous high power dissipation, current carrying and device interconnecting capability lead to selection of insulated metal substrate (IMS) as a substrate technology and electroplated eutectic solder bump as an interconnection technology. To develop robust processes capable of meeting high reliability in the automotive product environment, fundamental knowledge was needed about the behavior of the materials and interfaces in a flip chip assembly. This paper presents results of the parametric analysis of flip chip attach on IMS substrate. Impact of main variables, including die size, substrate thickness, underfill material, soldermask material and die passivation on the stress distribution and reliability in IMS assemblies was studied. The detailed stress analyses, materials compatibility and interface studies has resulted in a high level of process control and an excellent reliability performance.

Recent advances in optical devices, polymeric materials, and in the electronic MCM packaging and interconnect technologies could bring the cost of optical interconnect to a level affordable for module, board, and backplane level interconnect applications. Specifically, we discuss how the development in (1) vertical-cavity surface-emitting-laser devices, (2) multichip module packaging technologies, (3) optical polymers, and (4) adaptive interconnect can be applied to benefit optoelectronic packaging and interconnect. We show how these advancements will allow widely used planar processes and the already developed packaging technology in electronics to be applicable to optoelectronic packaging to reduce both recurring and nonrecurring engineering costs for this new technology insertion into computers and advanced electronic systems.

Small, light weight and multifunctional electronic components are attracting much attention because of the rapid growth of the wireless communication systems and microwave products in the consumer electronic market. The component manufacturers are thus forced to search for new advanced integration, packaging and interconnection technologies. One solution is the low temperature cofired ceramic (LTCC) technology enabling fabrication of three-dimensional ceramic modules with low dielectric loss and embedded silver electrodes. During the past 15 years, a large number of new dielectric LTCCs for high frequency applications have been developed. About 1000 papers were published and ∼500 patents were filed in the area of LTCC and related technologies. However, the data of these several very useful materials are scattered. The main purpose of this review is to bring the data and science of these materials together, which will be of immense help to researchers and technologists all over the world. The commercially available LTCCs, low loss glass phases and researched novel materials are listed with properties and references. Additionally, their high frequency and thermal performances are compared with the other substrate material options such as high sintering temperature ceramics and polymers, and further improvements in materials' development required are discussed.

This paper presents a printed organic complementary technology on flexible plastic substrate with high performance N and P-type Organic Thin Film Transistors (OTFTs), based on small-molecule organic semiconductors in solution. Challenges related to the integration of both OTFT types in a common complementary flow are addressed, showing the importance of surface treatments. Data on single devices and elementary complementary digital circuits (inverters and ring oscillators) are presented, demonstrating that a robust and reliable flow with high electrical performances can be established for printed organic devices.

In this paper, the research is focused on lifetime analysis and prediction of silver sintered power devices by experiment and numerical simulation. As researches are emerging on the field of lead-free interconnect technology, silver sintering become an alternative interconnect technology to standard solders. This technology differs from other interconnect technologies because of it’s improved thermal and mechanical properties. Aluminum cladded copper core (CucorAl) wires have been used to prevent early fail of top contacts. Material degradation due to thermal fatigue in the sintered silver still influences the reliability in the interconnect, in particular for high temperature swings upcoming with wide bandgap semiconductors. Plastic deformation is observed in sintered silver interconnect which depends on time and temperature. This research work presents combined experimental and finite element analysis (FEA) results for developing a lifetime model for the sintered silver power modules. Different parameters such as porosities on the sintered silver layer, substrates, plastic and creep constitutive laws, die thickness and sizes, should be considered during the development of lifetime model. In this investigation, Insulated-gate bipolar transistor (IGBT) chips are integrated on different substrates such as printed circuit board (PCB- Help H), insulated metal substrate (IMS), copper lead frame (Cu-lead frame) and direct copper bond (DCB) by silver sintered interconnect. Failure modes such as wire bond lift-off and die bond degradation are observed during this research.

Advanced heterogeneous integration (HI) technology is much needed for applications from edge to cloud to meet the stringent system-level requirements on performance, power, profile, cycle-time and cost (P3C2). In addition to 3DIC with TSV innovative packaging technologies such as silicon interposer (2.5D) and fan-out wafer-level-packaging (2D/3D) become new paradigm for the semiconductor industry to realize the system integration. In this paper, we will discuss the new trend of advanced packaging technology — a strong need for application-specific integration solutions. Many of those are proposed. The solution with higher performance at lower cost will prevail. Furthermore, the solutions that readily integrate multi-chip to enable chip-partition to extend Moore's Law effectively have long-term advantages.

The rapid advances in IC design and fabrication continue to challenge the electronic packaging technology, in terms of fine pitch, high performance, low cost and better reliability. In the near future, the demands for higher I/O count per integrated circuit (IC) chip increases as the shift towards the nano ICs with feature size less than 90nm. To meet the above requirements, the chip-to-substrate interconnection technologies with less than 100/spl mu/m pitch are required. Currently, the CTE mismatch between Si chip and substrate and assembly yield of such fine pitch interconnections serves as the biggest bottle neck issue. In this work a simple copper column based bed of nails-wafer level interconnects showing greater potentials in meeting some of these requirements for next-generation packaging is reported. The process development of fabricating the copper columns with various height and solder deposition on to the tip of the column is reported. This technology has been developed to meet fine pitch of 100 microns and high density interconnections. The development of a test chip demonstrator of 10 /spl times/ 10mm/sup 2/ with 3338 I/Os designed and fabricated for optimizing the process and the board level reliability test with out underfill performed under temperature cycling at range of -40/spl deg/C to 100/spl deg/C are also presented.

Packaging effect investigation of CMOS compatible pressure sensor using flip chip and flex circuit board technologies

Packaging technology is currently transition from flip chip technology to three dimensional integrated circuits (3D ICs) to meet the requirements of consumer electronic products. Compared to flip chip technology, the dimension of microbumps in 3D ICs is shrunk by a factor of 10. In this study, the behaviors of thermomigration in Pb-free solders of flip chip and 3D ICs are presented. When the bump height is 100 μm in the flip chip samples, the Sn protrusion was observed at the hot end and voids formation at the cold end. However, when the bump height is reduced to 5.8 μm in the 3D IC samples, no significant microstructural evolution of Sn was found; instead, the dissolution of Ni under-bump metallization at hot end was observed. We propose that discrepancy between flip chip solder joints and 3D IC microbumps is mainly attributed to the effect of back stress and the presence of thicker Ni under-bump metallization in the 3D IC packaging. Moreover, the critical temperature gradient in terms of different bump heights is discussed, showing below which there will be no net effect of thermomigration of Sn.

Several applications in the fields of industrial sensors and power electronics are creating a demand for high operating temperature of 300 °C or even higher. Due to the increased temperature range new potential defect risks and material interactions have to be considered. As a consequence, innovation in semiconductor, devices and packaging technologies has to be accompanied by dedicated research of the reliability properties. Therefore various investigations on realizing high temperature capable electronic systems have shown that a multidisciplinary approach is necessary to achieve highly reliable solutions. In the course of the multi-institute Fraunhofer internal research program HOT-300 several aspects of microelectronic systems running up to 300 °C have been investigated like SOI-CMOS technology and circuits, silicon capacitor devices, a capacitive micromachined ultrasonic transducer (CMUT), ceramic substrates and different packaging and assembly techniques. A ceramic molded package has been developed. Die attach on different leadframe alloys were investigated using silver sintering and transient liquid phase bonding (TLPB). Copper and gold wire bonding was studied and used to connect the chips with the package terminals. Investigations in flip chip technology were performed using Au/Sn and Cu/Sn solder bumps for transient liquid phase bonding. High operating temperatures result in new temperature driven mechanisms of degradation and material interactions. It is quite possible that the thermomechanical reliability is a limiting factor for the technology to be developed. Therefore investigations on material diagnostics, reliability testing and modeling have been included in the project, complementing the technology developments.