Flipped Voltage Follower Based Low Dropout (LDO) Voltage Regulators: A Tutorial Overview

With significant growth in portable multimedia devices such as smartphones, application processors (AP) play a critical role for running various multimedia applications on these devices. By considering the power constraints of such devices, we often integrate reconfigurable processors (RPs) into APs. This is because RPs offer flexibility and good performance, thereby greatly improving the power efficiency for running these multimedia applications. Like many other processors, RPs also exploit the dynamic voltage/frequency scaling (DVFS) to improve their power efficiency. Owing to the platform cost constraints, however, these RPs are often integrated to low dropout (LDO) voltage regulators (VRs) instead of switching VRs. When compared with switching VRs, LDO VRs are very inexpensive; however, they suffer from considerable power loss when they are required to deliver a low output voltage. However, many previous studies focused on analyzing the power efficiency of various DVFS techniques only with regard to the processors and did not consider the negative impact of the VR power losses on the overall power efficiency of the platform. In this work, we quantitatively compare the power efficiency of a Samsung RP (SRP) adopting the race-to-halt technique with that of the SRP exploiting the DVFS supported by LDO VRs, by considering the effect of the VR power losses. Finally, we demonstrate that using the race-to-halt technique results in high power efficiency when compared with the DVFS in a commercial processor, by considering the VR power efficiency.

In this paper, we present a pseudo-flash based digital low dropout (Digital LDO) voltage regulator. The novelty of our pseudo-flash based Digital LDO (PFD-LDO) voltage regulator lies in the fact that we use pseudo-flash (or alternately, flash) transistor subarrays for voltage regulation. By changing the threshold voltage (and thereby, the ON resistance) of these transistors, we can use the same design to meet different regulator specifications. The threshold voltage can be programmed either at the factory by the manufacturer or in the field by the user. This gives the manufacturer the ability to offer a family of LDO regulators with a single design, a significant economic advantage. In addition, aging effects and temperature variations are effectively erased since the threshold voltage of the pseudo-flash (or flash) transistors can be tuned to a fine degree in the field. Similarly, process variations can be cancelled after manufacturing in the factory. These advantages are absent in traditional LDO regulators. Our design uses two subarrays. A coarse subarray is used to reduce the recovery time and output voltage overshoot/undershoot, while a fine subarray regulates the output voltage, minimizing the output voltage ripple. Unlike state-of-the-art LDO regulators, our design can realize multiple specifications with the same circuit. For example, we demonstrate that the V<inf>out</inf> of the proposed PFD-LDO regulator can range from 0.7V to 1.7V when the supply voltage V<inf>IN</inf> ranges from 0.8V to 1.8V, using the same circuit design. Over this voltage range, the proposed PFD-LDO regulator achieves V<inf>shoot</inf> < 144mV, t<inf>rec</inf> < 0.41µs and V<inf>ripple</inf> < 7.3mV when the I<inf>max</inf> ranges from 15mA to 250mA.

This paper compares the performance of three low drop-out (LDO) voltage regulators (simple LDO, LDO with common-source, and LDO with source-follower) in load regulation and transient response. The regulators are designed in 1.6 /spl mu/m technology with three different error amplifier designs to investigate the regulating performance. The performance of each architecture is verified by simulation results.

Low dropout linear voltage regulators are analog circuit blocksthat play an important role in power delivery process and prevent a system from fluctuations in the supply rails.There is a high demand on using LDO regulator in system-on-chip (SOC) applications, given their inherently noisy environment.This work presents a design of low dropout voltage regulator (LDO) to satisfy desiredparameters. Basic design parameters of the proposed LDO CMOS circuit are introduced. The proposed circuit is designedto achieve a low quiescent current and dropout voltage as well as large PSRR value as possible, while maintaining the stability is paramount.Simulation results of the proposed circuit using 180 nm process CMOS technology and its corner analysis are presented. The simulation of the proposed LDO design achieveslow quiescent current in the range of microamperes.

A low dropout (LDO) voltage regulator with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented in this paper. Large 1µF off-chip load capacitor is used to achieve the high PSRR. However, this decreases the gain and pushes the LDO’s output pole to lower frequency causing the circuit to become unstable. The proposed LDO uses rail-to-rail folded cascode amplifier to compensate the gain and stability problems. 2nd order curvature characteristic is used in bandgap voltage reference circuit that is applied at the input of the amplifier to minimize the TC. The characteristic is achieved by implementing MOSFET transistors operate in weak and strong inversions. The LDO is designed using 0.18µm CMOS technology and achieves a constant 1.8V output voltage for input voltages from 3.2V to 5V and load current up to a 128mA at temperature between -40°C to 125°C. The proposed LDO is targeted for RF application which has stringent requirement on noise rejection over a broad range of frequency.

This article presents a high current radiation-hardened low-dropout (LDO) voltage regulator integrated in bipolar technology for space and other harsh radiation environment applications. The fabricated LDO consumes 70mA ground current at 7A maximum output current. The dropout voltage is 700mV at full load of 7A, improving efficiency and reducing power consumption. It has a maximum input voltage of 26V and provides an output voltage of 1.5 V, with output voltage accuracy of ±0.2%. The proposed LDO achieves a successful line regulation of 0.3%, and a load regulation of 0.2%. Through radiation hardened by circuit design, the LDO achieves SET immunity at linear energy transfer (LET) of 37.4 MeV•cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg.

In this paper, a different type of pulse width modulation (PWM) control scheme for a buck converter is introduced. The proposed buck converter uses PWM with frequency hopping and a low quiescent–current low dropout (LDO) voltage regulator with a power supply rejection ratio enhancer to reduce high spurs, harmonics and output voltage ripples. The low quiescent–current LDO voltage regulator is not described in this paper. A three-bit binary-to-thermometer decoder scheme and voltage ripple controller (VRC) is implemented to achieve low voltage ripple less than 3mV to increase the efficiency of the buck converter. An internal clock that is synchronized to the internal switching frequency is used to set the hopping rate. A center frequency of 2.5MHz was chosen because of the bluetooth low energy (BLE) application. This proposed DC-DC buck converter is available for low-current noise-sensitive loads such as BLE and radio frequency loads in portable communications devices. Thus, a high-efficiency and low-voltage ripple is required. This results in a less than 2% drop in the regulator’s efficiency, and a less than 3mV voltage ripple, with -26 dBm peak spur reduction operating in the buck converter.

An external capacitor-less low dropout (LDO) voltage regulator with high PSRR and enhanced transient response is presented. The novel idea is applying a replica circuit which can pull excessive current. Excessive Current Pulling (ECP) technique decreases the equivalent output impedance to enhance transient response. The proposed LDO has been simulated in 0.18 μm CMOS Technology. Its regulated output voltage is 1.6 V with the power supply of 1.8 V. The proposed technique has the advantages of simulated PSRR of −88.7 dB at 1 MHz and −67 dB at 100 KHz. Overshoots and undershoots are less than 45.2 mV and 30 mV under the load varies from 50 mA to 0 mA with rise/fall time of 100ns, respectively. Simulation results show that the achieved line regulation is 28.3 mV/V and the load regulation is 0.33 %/mA.

A low power low-dropout (LDO) voltage regulator with self-reduction quiescent current is proposed in this paper. This proposed capacitorless LDO for Silicon-on-Chip (SoC) application has introduced a self-adjustable low-impedance circuitry at the output of LDO to attain stability critically during low output load current (less than a few hundred of micro-ampere). When the LDO load current increases, it reduces the LDO output impedance and moved the pole towards higher frequency away from the dominant pole and improving the system stability. When this happen, less amount of quiescent current is needed for the low-impedance circuitry to sustain the low output impedance. In this proposed LDO, the quiescent current that been used to sustain the low output impedance will be self-reduced when the output load current increases. Thus, the reduction of quiescent current at low output load current has tremendously improved the efficiency. The simulation results have shown a promising stability at low load current 0~1mA. The dropout voltage for this LDO is only 100mV at 1.2V supply. The proposed LDO is validated using Silterra 0.13μm CMOS process model and designed with high efficiency at low output load current.

Low drop-out (LDO) voltage regulators are widely used in many portable applications, such as cell phones, laptops, and earplugs. However, the design and simulation of the circuit takes a long time. Hence, the behavioral model for an LDO regulator is greatly needed. In this paper, the hybrid modeling method has been illustrated for generating a behavioral model for an LDO regulator circuit. The hybrid modeling method integrates a table-based modeling method and a circuit simplification method for generating an LDO linear regulator behavioral model. Based on research of the automation topologies and algorithms a behavioral model generation tool for an LDO linear regulator, LDOCad, is also described, including the software architecture and different modules of LDOCad. This tool provides the modeler, or circuit designer, with an approach to quickly and automatically generate a behavioral model for an LDO linear regulator. When the netlist processing algorithm, the table generation algorithm, and the modeled node and topology device extraction algorithm are executed, the hybrid model can be generated through the model topology formulator. The algorithms are generic and robust. The models tested demonstrate an accurate match with the performance of the original circuits and achieve from a 5 to 19 times speed improvement in simulations.

Low dropout regulators (LDOs) are a simple and inexpensive way to regulate an output voltage that is powered from a higher voltage input [1]. An LDO regulator is a DC linear voltage regulator that can regulate the magnitude of the output voltage even when the supply voltage is very close to the output voltage. In this research paper, various building blocks of a CMOS-based low-dropout voltage regulator were designed and simulated using Multisim LIVE, an online circuit simulator. All of the building blocks were then combined to form the device. Based on the results of the simulation, several spesifications of the LDO were determined. Those are the LDO’s dropout voltage, its quiescent current, its load regulation, and its line regulation. At the end of the design process, during testing it can be shown that this LDO resulted in a dropout voltage of magnitude 200 mV at 200 mA load current which is quite a low dropout voltage. The design has a quiescent current of magnitude 300 , a load regulation of magnitude , and a line regulation of magnitude .

This paper describes a low-dropout (LDO) voltage regulator system for portable device applications, with a capacitorless output. The regulator operates with supply voltages from 1.6V to 2V, providing 0.9V to 1.4V regulated voltages at a 99.2% current efficiency. The fully integrated architecture with a 100pF integrated decoupling capacitor was implemented in IBM 130nm CMOS technology, allowing greater power system integration. Post-layout simulations of our design demonstrate that the proposed LDO architecture provides a fast load regulation with a fast 320ns response time for 100mA load current and regulated voltage variations of less than 25mV.

Abstract. Low-dropout (LDO) voltage regulators are widely used to supply low-voltage digital circuits. For recent ultra-low-power microcontroller systems, a fully-integrated LDO without any external capacitance is preferred in order to achieve a fast and energy-efficient wake-up. Commonly, an LDO is specified, designed and verified for DC load currents. In contrast, a digital load creates large current spikes. As an LDO designed for low quiescent current is too slow to react on fast current spikes, a minimum on-chip capacitance is required to keep the supply voltage within a certain error window. Different fully-integrated LDO topologies are investigated regarding their suitability to supply low-voltage digital circuits. The any-load stable LDO topology is selected and implemented on a 0.13 μm test-chip. The LDO is able to provide a maximum load current of 2.5 mA while consuming a quiescent current of 17 μA.

This paper discusses and address a transistor based new current control low dropout voltage regulator (LDO) offering a high gain and large bandwidth without using complex compensation and large output capacitor. The conventional error amplifier based LDO which is using voltage feedback loop suffers from an inherent poor load transient response. The poor load transient associated with error amplifier results because of limited DC open-loop gain and limited closed loop bandwidth. The frequency response of error amplifier based LDO is highly sensitive to load current. Current controlled transistor based LDO has been designed for fast dynamic response with low output capacitor in the range of 1 to 10 uF. Experimental results show circuit has small output voltage variations of less than 10 mV for load current variation in the range of 0–3A without any overshoot or undershoot. This circuit is also simulated in PSpice and results are compared with Hardware LDO.

Mobile phones require linear voltage regulators with low drop-out, high PSRR, cost efficient and low ground current. They need to pass steady output under all load conditions. Preferably, one gadget would have all these aspects and one low-dropout voltage regulator (LDO) could be utilized in a mobile phone. But in practice, the various mobile phone blocks are powered by LDOs with distinct performance aspects. The proposed LDO is processed in a standard 0.18µm CMOS process. The regulator can settle the output to a stable voltage within 3.7µs. The line regulation, load regulation and PSRR of the proposed regulator are 0.188% and 0.0755%, −54dB respectively.