Flow-through tensors: A unified computational graph architecture for multi-layer transportation network optimization

Creating resilient and multi-layered transportation networks is of paramount importance for modern society, particularly considering the need to respond to a diverse array of risks. These resilient multilayer transport networks appear to share comparable properties with vital multilayer distribution systems found onboard large and complex ships. However, little is currently known regarding the similarities and differences in the design of multilayer networks found in various contexts, such as transportation infrastructure and shipboard distribution systems. This study introduces several multi-modal networks and elucidates their similarities and differences and their design processes. A case study details a typical topology of integrated onboard distribution systems, represented abstractly as a multilayer network to showcase said similarities and differences. The study concludes with the lessons learned from comparing transportation networks with vital onboard distribution systems and provides an outlook for future research into resilient shipboard systems.

The recent progress in Machine Learning (Géron, 2022) and particularly Deep Learning (Goodfellow, 2016) models exposed the limitations of traditional computer architectures. Modern algorithms demonstrate highly increased computational demands and data requirements that most existing architectures cannot handle efficiently. These demands result in training speed, inference latency, and power consumption bottlenecks, which is why advanced methods of computer architecture optimization are required to enable the development of ML/DL-dedicated efficient hardware platforms (Engineers, 2019). The optimization of computer architecture for applications of ML/DL becomes critical, due to the tremendous demand for efficient execution of complex computations by Neural Networks (Goodfellow, 2016). This paper reviewed the numerous approaches and methods utilized to optimize computer architecture for ML/DL workloads. The following sections contain substantial discussion concerning the hardware-level optimizations, enhancements of traditional software frameworks and their unique versions, and innovative explorations of architectures. In particular, we discussed hardware including specialized accelerators, which can improve the performance and efficiency of a computation system using various techniques, specifically describing accelerators like CPUs (multicore) (Hennessy, 2017), GPUs (Hwu, 2015) and TPUs (Contributors, 2017), parallelism in multicore architectures, data movement in hardware systems, especially techniques such as caching and sparsity, compression, and quantization, other special techniques and configurations, such as using specialized data formats, and measurement sparsity. Moreover, this paper provided a comprehensive analysis of current trends in software frameworks, Data Movement optimization strategies (A.Bienz, 2021), sparsity, quantization and compression methods, using ML for architecture exploration, and, DVFS (Hennessy, 2017),, which provides strategies for maximizing hardware utilization and power consumption during training, machine learning, dynamic voltage, and frequency scaling, runtime systems. Finally, the paper discussed research opportunity directions and the possibilities of computer architecture optimization influence in various industrial and academic areas of ML/DL technologies. The objective of implementing these optimization techniques is to largely minimize the current gap between the computational needs of ML/DL algorithms and the current hardware’s capability. This will lead to significant improvements in training times, enable real-time inference for various applications, and ultimately unlock the full potential of cutting-edge machine learning algorithms.

This study introduces the multilayer modular fusion graph attention network (MMF-GAT), an interpretable predictive framework that combines principles from network science and sociology to forecast infection risk. The model is based on the premise that infection risk is influenced by an individual’s overlapping membership across various social groups and their participation in shared activities that function as interaction hubs. To represent this complex social fabric, the framework formalizes a multilayer social graph that is assumed to be composed of personal contact, household, and community layers via fourth-order tensor formalism. The MMF-GAT architecture employs layer-specific graph attention network (GAT) modules to preserve context-specific modularity, combined with a late-fusion mechanism that represents how individuals connect different social settings. This approach operationalizes key sociological concepts by processing each layer independently before integration. When applied to a COVID-19 surveillance dataset of 2,264 individuals from Houston, Texas, the MMF-GAT model significantly outperformed five baseline models, achieving an accuracy of 0.78, an area under the curve (AUC) of 0.90, an F1 score of 0.72, and a precision‒recall area under the curve (PRAUC) of 0.89. Explainable AI (XAI) analysis identified structural features, particularly household degree, degree of personal contact, and affiliation with educational centers, as the most influential predictors. Owing to its robust predictive accuracy, the model effectively identifies high-risk individuals and settings, positioning it as a valuable tool for public health operations. This study makes a dual contribution. First, it advances multilayer network science through a novel computational architecture that preserves modularity. Second, it provides a validated, high-performance tool for public health informatics. This computational tool can support targeted interventions by optimizing contact tracing prioritization and resource allocation.

Topology analysis of Lanzhou public transport network based on double-layer complex network theory

This paper examines the performance potential of decoupled computer architectures on real-world codes, and includes the first performance bounds calculations to be published for the highly-decoupled ACRI-1 computer architecture. It also constitutes the first published work to report on the effectiveness of a decoupling Fortran90 compiler. Decoupling is an architectural optimisation which offers very high sustained performance through large-scale latency hiding. This paper investigates the applicability of access and control decoupling to real-world codes. We illustrate this with compiler-generated decoupling optimisations for the Perfect Club benchmark suite on the Advanced Computer Research Institute's ACRI-1 system, utilising the frequency of loss of decoupling (LOD) events as a measure of the effectiveness of decoupling to each code. We derive bounds for the performance of these codes and show that, whilst some exhibit performance roughly equivalent to that on vector computers, others exhibit considerably higher performance potential in a decoupled system.

The success of autonomous mobile robots depends on the ability to understand continuously changing scenery. Present techniques for analysis of images are not always suitable because in sequential paradigm, computation of visual functions based on absolute values of stimuli is inefficient. Important aspects of visual information are encoded in discontinuities of intensity, hence a representation in terms of relative values seems advantageous. We present the computing architecture of a massively parallel vision module which optimizes the detection of relative intensity changes in space and time. Visual information must remain constant despite variation in ambient light level or velocity of target and robot. Constancy can be achieved by normalizing motion and lightness scales. In both cases, basic computation involves a comparison of the center pixels with the context of surrounding values. Therefore, a similar computing architecture, composed of three functionally-different and hierarchically-arranged layers of overlapping operators, can be used for two integrated parts of the module. The first part maintains high sensitivity to spatial changes by reducing noise and normalizing the lightness scale. The result is used by the second part to maintain high sensitivity to temporal discontinuities and to compute relative motion information. Simulation results show that response of the module is proportional to contrast of the stimulus and remains constant over the whole domain of intensity. It is also proportional to velocity of motion limited to any small portion of the visual field. Uniform motion throughout the visual field results in constant response, independent of velocity. Spatial and temporal intensity changes are enhanced because computationally, the module resembles the behavior of a DOG function.

Although the design of many kinds of microprocessors has been under developing for several decades, the computer architecture R&D community lacks well documented lessons and experiences about design decisions in the research literature. In this paper, we systematically present the design decisions we made during the designing and prototyping of Godson-2 series processors. The 250MHz Godson-2B, 450MHz Godson-2C, and 1GHz Godson-2E processors that implement 64-bit, four-issue, out-of-order architecture were taped out in 2003, 2004, and 2005, respectively. Each processor triples its predecessor in the SPEC CPU2000 rates. Our first-hand experiences and lessons gained from these designs would provide unique perspectives and insights that are not available in any existing text books and/or published papers. We summarize 10 critical lessons and experiences based on hundreds of our attempts at architectural and design optimizations for performance improvement of Godson-2 series processors. The issues include silicon-simulation correlation, design balancing, performance optimizing, and pico-architecture tuning. We conclude that persistent improvement, attitude towards work-on-silicon design, and insightful understanding of software and fabrication process are the three most important factors for designing a high performance processor with low energy consumption.

Previous work on analog VLSI implementation of multilayer perceptrons with on-chip learning has mainly targeted the implementation of algorithms such as back-propagation. Although back-propagation is efficient, its implementation in analog VLSI requires excessive computational hardware. It is shown that using gradient descent with direct approximation of the gradient instead of back-propagation is more economical for parallel analog implementations. It is shown that this technique (which is called ;weight perturbation') is suitable for multilayer recurrent networks as well. A discrete level analog implementation showing the training of an XOR network as an example is presented.

An optimal unified architecture that can efficiently compute the discrete cosine, sine, Hartley, Fourier, lapped orthogonal, and complex lapped transforms for a continuous input data stream is proposed. This structure uses only half as many multipliers as the previous best known scheme. The proposed architecture is regular, modular, and locally connected. In the realisation of the discrete cosine transform, only 2N-2 multipliers are needed. A theoretical justification is provided showing that any discrete transform whose basic functions satisfy the fundamental recurrence formula has a second-order autoregressive structure in its filter realization. It is also demonstrated that dual generation transform pairs share the same autoregressive structure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Computing the inverse of a number in finite fields GF(p) or GF(2n) is equally important for cryptographic applications. In this paper four optimized Montgomery inverse algorithms are proposed to achieve high speed and flexibility. Then a novel scalable and unified architecture for Montgomery inverse hardware that operates in both GF(p) and GF(2n) is proposed. The scalable design is the novel modification performed on the fixed hardware to make it occupy a small area and operate with better or similar speed, and it takes less number of clock cycle as the datapath of scalable design is large and can also achieve high clock frequency. Finally this work has been verified by modeling it in Verilog-HDL, implementing it under 0.18µm SMIC technology. The result indicates that our work has advanced performance than other works.

The increasing demand for computing power and the emergence of heterogeneous computing architectures have driven the exploration of innovative techniques to address current limitations in both the compute and memory subsystems. One such solution is the use of Accelerated Processing Units (APUs), processors that incorporate both a central processing unit (CPU) and an integrated graphics processing unit (iGPU). However, the performance of both APU and CPU systems can be significantly hampered by address translation overhead, leading to a decline in overall performance, especially for cache-resident workloads. To address this issue, we propose the introduction of a new intermediate address space (IAS) in both APU and CPU systems. IAS serves as a bridge between virtual address (VA) spaces and physical address (PA) spaces, optimizing the address translation process. In the case of APU systems, our research indicates that the iGPU suffers from significant translation look-aside buffer (TLB) misses in certain workload situations. Using an IAS, we can divide the initial address translation into front- and back-end phases, effectively shifting the bottleneck in address translation from the cache side to the memory controller side, a technique that proves to be effective for cache-resident workloads. Our simulations demonstrate that implementing IAS in the CPU system can boost performance by up to 40% compared to conventional CPU systems. Furthermore, we evaluate the effectiveness of APU systems, comparing the performance of IAS-based systems with traditional systems, showing up to a 185% improvement in APU system performance with our proposed IAS implementation. Furthermore, our analysis indicates that over 90% of TLB misses can be filtered by the cache, and employing a larger cache within the system could potentially result in even greater improvements. The proposed IAS offers a promising and practical solution to enhance the performance of both APU and CPU systems, contributing to state-of-the-art research in the field of computer architecture.

&lt;div class="section abstract"&gt;&lt;div class="htmlview paragraph"&gt;As the technology in autonomous vehicle and smart city infrastructure is developing fast, the idea of smart city and automated driving has become a present and near future reality. Both Highway Chauffeur and low speed shuttle applications are tested recently in different research to test the feasibility of autonomous vehicles and automated driving. Based on examples available in the literature and the past experience of the authors, this paper proposes the use of a unified computing, sensing, communication and actuation architecture for connected and automated driving. It is postulated that this unified architecture will also lead to a scalable and replicable approach. Two vehicles representing a passenger car and a small electric shuttle for smart mobility in a smart city are chosen as the two examples for demonstrating scalability and replicability. For this purpose, the architecture in the passenger car is transferred to the small electric vehicle and used in its automation for demonstrating both scalability and replicability. High Level control and low level lateral control are presented in this paper. The parameter space based parametric control design approach that we are using to achieve scalable automated driving controllers is presented in the paper along with a discussion of how to evaluate performance and a brief description of the planned proof-of-concept test deployment.&lt;/div&gt;&lt;/div&gt;

The emerging applications is the dominant factor that drives the evolvement of computer technologies and architectures. Among the emerging applications these days, neural networks are the most attention-grabbing one. To unleash the benefits of neural network, the architecture optimization is a necessity. In this paper, the architecture requirements of neural network is first reviewed. Then based on these requirements, how to utilize 3D IC techniques to design emerging architectures is given with the introduction of state-of-art studies.

Developing an evolving multi-layer perceptron network by genetic algorithm to predict full-scale ‎municipal ‎wastewater treatment plant effluent

Molecular dynamics models of tubulin tetramers in complex with the anticancer drug taxol were created based on high-resolution spatial structures (PDB ID 3J6G). We tested performance of various computational architectures in molecular dynamics calculations of tubulin tetramers. We revealed the optimal computer architecture and carried out three 1 μs molecular dynamic trajectories of taxol-bound tubulin tetramer. We analyzed the conformational flexibility of tubulin tetramers in a complex with taxol, calculated the Euler angles for intra- and inter-dimer interfaces of the protofilament, as well as the degree and direction of protofilament bending. The stiffness of protofilaments was studied using the energy equipartition theorem. The results allowed us to conclude that taxol binding reduces stiffness at both the inter- and intra-dimer interfaces, which may facilitate the process of microtubule assembly.