Folding Active List for High Performance and Low Power

Large instruction window processors achieve high performance by exposing large amounts of instruction level parallelism. However, accessing large hardware structures typically required to buffer and process such instruction window sizes significantly degrade the cycle time. This paper proposes a novel checkpoint processing and recovery (CPR) microarchitecture, and shows how to implement a large instruction window processor without requiring large structures thus permitting a high clock frequency.We focus on four critical aspects of a microarchitecture: (1) scheduling instructions, (2) recovering from branch mispredicts, (3) buffering a large number of stores and forwarding data from stores to any dependent load, and (4) reclaiming physical registers. While scheduling window size is important, we show the performance of large instruction windows to be more sensitive to the other three design issues. Our CPR proposal incorporates novel microarchitectural schemes for addressing these design issues---a selective checkpoint mechanism for recovering from mispredicts, a hierarchical store queue organization for fast store-load forwarding, and an effective algorithm for aggressive physical register reclamation. Our proposals allow a processor to realize performance gains due to instruction windows of thousands of instructions without requiring large cycle-critical hardware structures.

Modern microprocessors achieve high application performance at the acceptable level of power dissipation. In terms of power to performance trade-off, the instruction window is particularly important. This is because enlarging the window size achieves high performance but naive scaling of the conventional instruction window can severely increase the complexity and power consumption. In this paper, we propose low-power instruction window techniques for contemporary microprocessors. First, the separated reorder buffer (SROB) reduces power dissipation by deferred allocation and early release. The deferred allocation delays the SROB allocation of instructions until their all data dependencies are resolved. Then, the instructions are executed in program order and they are released faster from the SROB. This results in higher resource utilization and low power consumption.

A low power voltage management technique is proposed to reduce power consumption for domino circuits. Exploiting a rising and charge-sharing voltage allow the domino circuits to have both high performance and low power consumption. A test chip has been successfully validated to achieve 68% dynamic power consumption and 15% static power consumption respectively using TSMC 0.13um CMOS technology.

Gorilla is a methodology for generating FPGA-based solutions especially well suited for data parallel applications with fine grain irregularity. Irregularity simultaneously destroys performance and increases power consumption on many data parallel processors such as General Purpose Graphical Processor Units (GPGPUs). Gorilla achieves high performance and low power through the use of FPGA-tailored parallelization techniques and application-specific hardwired accelerators, processing engines, and communication mechanisms. Automatic compilation from a stylized C language and templates that define the hardware structure coupled with the intrinsic flexibility of FPGAs provide high performance, low power, and programmability.Gorilla's capabilities are demonstrated through the generation of a family of core-router network processors processing up to 100Gbps (200MPPS for 64B packets) supporting any mix of IPv4, IPv6, and Multi-Protocol Label Switching (MPLS) packets on a single FPGA with off-chip IP lookup tables. A 40Gbps version of that network processor was run with an embedded test rig on a Xilinx Virtex-6 FPGA, verifying for performance and correctness. Its measured power consumption is comparable to full custom, commercial network processors. In addition, it is demonstrated how Gorilla can be used to generate merged virtual routers, saving FPGA resources.

Modern client processors typically use one of three commonly-used power delivery network (PDN) architectures: 1) motherboard voltage regulators (MBVR), 2) integrated voltage regulators (IVR), and 3) low dropout voltage regulators (LDO). We observe that the energy-efficiency of each of these PDNs varies with the processor power (e.g, thermal design power (TDP) and dynamic power-state) and workload characteristics (e.g., work-load type and computational intensity). This leads to energy-inefficiency and performance loss, as modern client processors operate across a wide spectrum of power consumption and execute a wide variety of workloads. To address this inefficiency, we propose FlexWatts, a hybrid adaptive PDN for modern client processors whose goal is to provide high energy-efficiency across the processor's wide range of power consumption and workloads. FlexWatts provides high energy-efficiency by intelligently and dynamically allocating PDNs to processor domains depending on the processor's power consumption and workload. FlexWatts is based on three key ideas. First, FlexWatts combines IVRs and LDOs in a novel way to share multiple on-chip and off-chip resources and thus reduce cost, as well as board and die area overheads. This hybrid PDN is allocated for processor domains with a wide power consumption range (e.g., CPU cores and graphics engines) and it dynamically switches between two modes: IVR-Mode and LDO-Mode, depending on the power consumption. Second, for all other processor domains (that have a low and narrow power range, e.g., the IO domain), FlexWatts statically allocates off-chip VRs, which have high energy-efficiency for low and narrow power ranges. Third, FlexWatts introduces a novel prediction algorithm that automatically switches the hybrid PDN to the mode (IVR-Mode or LDO-Mode) that is the most beneficial based on processor power consumption and workload characteristics. To evaluate the tradeoffs of PDNs, we develop and open-source PDNspot, the first validated architectural PDN model that enables quantitative analysis of PDN metrics. Using PDNspot, we evaluate FlexWatts on a wide variety of SPEC CPU2006, graphics (3DMark06), and battery life (e.g., video playback) workloads against IVR, the state-of-the-art PDN in modern client processors. For a 4 W thermal design power (TDP) processor, FlexWatts improves the average performance of the SPEC CPU2006 and 3DMark06 workloads by 22% and 25%, respectively. For battery life workloads, FlexWatts reduces the average power consumption of video playback by 11% across all tested TDPs (4W-50W). FlexWatts has comparable cost and area overhead to IVR. We conclude that FlexWatts provides high energy-efficiency across a modern client processor's wide range of power consumption and wide variety of workloads, with minimal overhead.

A flip-flop using a combination of thin and thick gate transistors combines high performance and low standby power. Setup and hold times are controlled by the master latch implemented in high performance transistors, while a thick gate slave latch provides state retention at low standby power when the high performance circuit power supply is gated off. The design has reduced circuit and power-down control complexity compared to previously described circuits using thick gate shadow latches for low standby power state storage. Measured test chip results on a foundry 130 nm process prove the viability of the design. The thick gate shadow latches are shown to have good retention capability at low supply voltages, suggesting that reduced shadow latch supply voltage during standby will be effective at mitigating the drain to bulk leakage components that are increasingly limiting for low power standby modes.

Solid state disks (SSDs) consisting of NAND flash memory are replacing conventional HDDs in mobile and server markets. The major reason for such a widespread replacement is the high performance and low power consumption enabled by an SSD. It especially gives better performance and power efficiency for random requests, because it does not require slow-moving and power-hungry mechanical operations, e.g., motor control. For the performance of sequential requests, multi-channel/way parallel architectures are adopted, and the speed of the host interface is increased. Even though an SSD has better power efficiency than an HDD, the SSD power consumption must be minimized due to the stringent power consumption constraints of mobile and server products. This chapter presents a case study of developing an SSD power model with an application to low power SSD design. The power model is based on real measurement data. For accurate modeling, one must take into account the internal parallelism as well as power states. The case study shows that the power model is useful in evaluating the designs of dynamic power management policy.

This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the previous generation, especially PMOSFET has demonstrated an astonishing 35 % performance enhancement from the previous technology node

Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines. Selective re-execution is a technique that can reduce the penalty of mis-speculations by re-executing only instructions affected by the mis-speculation, instead of all instructions. In this paper we introduce a new selective re-execution mechanism that exploits the properties of a dataflow-like Explicit Data Graph Execution (EDGE) architecture to support efficient mis-speculation recovery, while scaling to window sizes of thousands of instructions with high performance. This distributed selective re-execution (DSRE) protocol permits multiple speculative waves of computation to be traversing a dataflow graph simultaneously, with a commit wave propagating behind them to ensure correct execution. We evaluate one application of this protocol to provide efficient recovery for load-store dependence speculation. Unlike traditional dataflow architectures which resorted to single-assignment memory semantics, the DSRE protocol combines dataflow execution with speculation to enable high performance and conventional sequential memory semantics. Our experiments show that the DSRE protocol results in an average 17% speedup over the best dependence predictor proposed to date, and obtains 82% of the performance possible with a perfect oracle directing the issue of loads.

Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines. Selective re-execution is a technique that can reduce the penalty of mis-speculations by re-executing only instructions affected by the mis-speculation, instead of all instructions. In this paper we introduce a new selective re-execution mechanism that exploits the properties of a dataflow-like Explicit Data Graph Execution (EDGE) architecture to support efficient mis-speculation recovery, while scaling to window sizes of thousands of instructions with high performance. This distributed selective re-execution (DSRE) protocol permits multiple speculative waves of computation to be traversing a dataflow graph simultaneously, with a commit wave propagating behind them to ensure correct execution. We evaluate one application of this protocol to provide efficient recovery for load-store dependence speculation. Unlike traditional dataflow architectures which resorted to single-assignment memory semantics, the DSRE protocol combines dataflow execution with speculation to enable high performance and conventional sequential memory semantics. Our experiments show that the DSRE protocol results in an average 17% speedup over the best dependence predictor proposed to date, and obtains 82% of the performance possible with a perfect oracle directing the issue of loads.

With the development of information technology, integrated circuits (IC) and system which target high performance and low power consumption have widely penetrated to all the aspects of national economy, national defense construction and people’s life. With the continuous increase in IC integration density, the power consumption is becoming the limiting factor. It turns out that the driving force of the future IC and system development is the reduction of the power consumption and improvement of the performance/power ratio. The Moore’s Law is inherently the law for the technology and economic development, and has served as the guideline of the IC development for half a century. However, with the scaling down of IC feature size and the corresponding increased integration density, it is progressively approaching the physical limitation. Moore’s Law will gradually complete its historic mission and it will be replaced by a law of reducing the power consumption while ensuring the performance requirements for IC, SoC and SiP performance, law of improving the performance/power ratio. This paper will discuss the related research topics on Green micro/nanoelectronics, including low-power design, novel low-power devices, manufacturing processes for low power applications and related micro/nano electromechanical systems.

Now a days in VLSI, System on Chip (SoC) design is replacing the systems on board due to its high performance, less area and low power. Though Complementary Metal Oxide Semiconductor (CMOS) devices are playing a key role in the realization of low power million transistor circuits are not useful in sub-threshold region due to their charge leakage. The major abnormalities of these devices are jitter, skew and high power consumption which is amplified in Radio Frequency (RF) range. This paper deals with the realization of a Real Time RF Clock Generator circuit implemented with Carbon Nano Tube Field Effect Transistor (CNTFET) and Fin Field Effect Transistor (FINFET) devices is considered for clocking digital circuits in RF range. RF clock uses differential amplifier with buffer signal, provides less offset frequency, fast data transmission, susceptible at low voltage level and reduce jitter. The power dissipation, area and performance of these circuits are compared with the CMOS circuits with power supply of 1.8v and frequency of 2 MHz. It is observed that —% power, —% of area and —% of delay are reduced.

In this paper, a graded channel doping paradigm is proposed to improve the nanoscale double gate junctionless DGJL MOSFET electrical performance. A careful mechanism study based on numerical investigation and a performance comparison between the proposed and conventional design is carried out. The device figures-of-merit, governing the switching and leakage current behavior are investigated in order to reveal the transistor electrical performance for ultra-low power consumption. It is found that the channel doping engineering feature has a profound implication in enhancing the device electrical performance. Moreover, the impact of the high-k gate dielectric on the device leakage performance is also analyzed. The results show that the proposed design with gate stacking demonstrates superior $$I_{{\textit{ON}}}/I_{{\textit{OFF}}}$$ ratio and lower leakage current as compared to the conventional counterpart. Our analysis highlights the good ability of the proposed design including a high-k gate dielectric for the reduction of the leakage current. These characteristics underline the distinctive electrical behavior of the proposed design and also suggest the possibility for bridging the gap between the high derived current capability and low leakage power. This makes the proposed GCD-DGJL MOSFET with gate stacking a potential alternative for high performance and ultra-low power consumption applications.

To solve the problems of insufficient acceleration capability and high power consumption of the existing embedded terminal target detection, a multi-strategy optimization hardware accelerator based on the YOLOv2 model is designed by taking advantage of the high concurrency characteristics of the CPU+FPGA structure. The accelerator improves its parallelism and real-time performance while reducing power consumption and resource consumption through floating-point quantization, adder optimization, and various HLS optimization strategies. Tested on Xilinx’s PYNQ-Z2 platform, the overall computing power of the accelerator reaches 27.1GOP/s, the average detection accuracy is 80.6%, and the overall power consumption is 2.609W. Compared with CPU and GPU, the obtained accuracy only loses 2%, but the power consumption is greatly reduced. It has strong practical significance in edge target detection that requires high real-time performance and low power consumption.

Their is significantly growing interests in a polymer electrolyte membrane fuel cell (PEMFC)as a promising alternative electric power generation system for stationary, backup power, and automotive applications because of high power density, low operating temperature, and reduced release of environmental pollutants relative to converntional energy conversion and storage devices [1]. In this regard, a high level of activities in materials science and engineering research for the PEMFC have been made to realize its potential applications as the advanced sustainable energy sourcecs.For realizing the widespread commercialization of the PEMFC, there are still technical hurdles including high cost, performance loss, and insufficient durability with long-term cycles [2]. Especially in automotive condition, startup/shutdown and load-cycling cause a significant degradation of Pt nanoparticles supported on high surface area carbon. Although several types of Pt-based catalysts with enhanced catalytic activity and/or durability have emerged, they are still in development [3]. Therefore,it is still of great importance to develop efficient electro-catalysts with enhancing stability as well as sustaining catalytic acitvity under the wide ranges of operating conditions.The development of a functional carbon supported Pt catalyst that has both high oxygen reduction activity and high durability would significantly contribute to the commercialization of automotive PEMFC. Herein we report a diazonium-functionalized graphitized carbon (DFGC) support prepared by grafting different types of end-functional groups on a GC support via simple diazonium chemistry that can improve the dispersion of Pt nanoparticles and reduce their sintering phenomena, resulting in higher electrochemical durability with enhanced catalytic activity as compared to the unmodified GC support. The membrane-electrode assembly (MEA) fabricated with the Pt/DFGC series as the cathode catalysts shows a power density higher than 1.0 W/cm2 under an automotivce operating condition at a low catalyst loading of 0.25 mgPt/cm2. The durability of the MEA was measured by electrocatalyst cycling and catalytst support cycling tests according to the procedures of DOE-FCTT accelerated stress test (AST) protocols. THe AST results reveal that the MEA series with the Pt/DFGC catalysts exhibit higher durability event at 30% lower catalyst loading compared to a commercial MEA. These results demonstrate that the catalyst design strategy based on simple diazonium chemistry is an effective way to fabricate highly durable catalysts with enhanced catalytic activity for the PEMFC, providing a design guide of a high performance MEA for automotive applications.We also present current development status of our developed MEA for automotive applications. Our research and development focus on the fabrication of a cost-competitive MEA with high power performance and longer durability even at lower Pt amount for automotive PEMFC systems. To achieve these goals, a high level of activities have been made to develop the MEA design for high temperature and low humidified operation including the design of highly active catalyst layer, the functionalization of polymer electrolyte membrane and interfaces in the MEA, and cost-effective manufacturing process. The development of a cost-competitive MEA with high power output, long durability, and operation flexibility is expected to contribute the widespread commercialization of automotive PEMFC systems. Further development of the MEA for automotive applications would be performed by balancing high performance against long-term durability and manufacturing cost.