FPGA-Based Hardware Implementation of Computationally Efficient Multi-Source DOA Estimation Algorithms

The type of Field Programmable Gate Arrays (FPGAs) technology and device family used in a design is a key factor for system reliability. Though antifuse-based FPGAs are widely used in aerospace because of their high reliability, current antifuse-based FPGA devices are expensive and leave no room for mistakes or changes since they are not reprogrammable. The substitute for antifuse-based FPGAs are needed in aerospace design, they should be both reprogrammable and highly reliable to Single Event Upset effects (SEUs). SRAM-based FPGAs are widely and systematically used in complex embedding digital systems both in a single chip industry and commercial applications. They are reprogrammable and high in density because of the smaller SRAM cells and logic structures. But the SRAM-based FPGAs are especially sensitive to cosmic radiation because the configuration information is stored in SRAM memory. The ideal FPGA for aerospace use should be high-density SRAM-based which is also insensitive to cosmic radiation induced SEUs. Therefore, in order to enable the use of SRAM-based FPGAs in safety critical applications, new techniques and strategies are essential to mitigate the SEU errors in such devices. In order to improve the reliability of SRAM-based FPGAs which are very sensitive to SEU errors, techniques such as reconfiguration and Triple Module Redundancy (TMR) are widely used in the aerospace electronic systems to mitigate the SEU and Single Event Functional Interrupt (SEFI) errors. Compared to reconfiguration and triplication, scrubbing and partial reconfiguration will utilize fewer or even no internal resources of FPGA. What's more, the detection and repair process can detect and correct SEU errors in configuration memories of the FPGA without affecting or interrupting the proper working of the system while reconfiguration would terminate the operation of the FPGA. This paper presents a payload system realized on Xilinx Virtex-4 FPGA which mitigates SEU effects in the internal FPGA by implementing scrubbing strategy and thus improve the reliability of the whole system.

Matrix operations form the core of array signal processing algorithms such as those required for direction of arrival (DOA) angle estimation of radio frequency signals incident on an antenna array. In this paper, we present a performance comparison of matrix decomposition methods for efficient FPGA hardware implementation of DOA estimation algorithms. These methods are very important in subspace-based DOA estimation algorithms as they are used for signal space extraction. DOA estimation algorithms employing LU, LDL, Cholesky, and QR decomposition methods are implemented on a Xilinx Virtex-5 FPGA. These DOA estimation algorithms are simulated in LabVIEW as well as experimentally validated in real-time on a prototype testbed constructed using Universal Software Radio Peripheral (USRP) Software Defined Radio (SDR) platform from National Instruments. Performance comparison of these algorithms is made in terms of resources consumption, computation speed, and estimation accuracy.

FIR (Finite Impulse Response) filters are often used in digital signal processing. This paper presents architecture for FIR filters on Xilinx Virtex FPGAs (field programmable gate arrays). The architecture is particularly useful for handling the problem of signal boundaries filtering, which occurs in finite length signal processing (e.g. image processing). Based on a bit parallel arithmetic, our architecture is fully scalable and parameterized. It cleverly exploits the Shift Register Logic (SRL16) component of the Virtex family. The implementation leads to considerable area savings compared to the conventional implementation (based on a hard router) with no speed penalty. A case study based on the implementation of the standard low filter of the Daubechies-8 wavelet on Xilinx Virtex-E FPGAs is presented.

Conventional seismic processing is performed on a CPU with 32 or 64-bit precision for all operations. In certain cases, using a reduced precision produces equivalent result within acceptable tolerances. However, as CPUs do not support configurable bit-widths, reducing precision brings no benefits to performance. In contrast, Field Programmable Gate Arrays (FPGA) enable application specific number representations. With hardware support for reconfigurable number format and bit-width, reduced precision can greatly decrease the area cost and I/O bandwidth of the design, thus multiplying the performance with concurrent processing cores on an FPGA. In this paper, we present a tool to determine the most appropriate number format for a given seismic application. We demonstrate the methodology on a source-receiver downward continuous based migration. The acceleration device is a Maxeler Technologies MAX-1 card containing a Xilinx Virtex-4 FPGA and connects to a PC over a PCI Express bus. Using optimized number representations, we can implement two concurrent processing cores on the FPGA, and achieve a speedup of 14 times compared to a Intel Xeon 1.86GHz CPU. Moreover, with sufficient bandwidth between the CPU and FPGA, we show that a further increase to 48x speedup is possible.

The Universal Software Radio Peripheral (USRP) from Ettus Research is a software defined radio (SDR) that has emerged as an affordable and capable radio used in both teaching and research applications. Despite its widespread use, precise specification of the transmit power of USRP SDR boards is not readily available in the manufacturer data sheets, and in this paper we present an experimental study of the transmit power for the B-series USRP SDR board from Ettus Research. Specifically, a USRP B200 SDR is used to setup extensive measurements of the output transmit power over its covered frequency range and the power variation with frequency along with its dependence on the transmit gain parameter in the USRP hardware driver (UHD) is evaluated. A discussion of the possible causes that lead to variations in the transmit power is also presented.

Content-addressable memory (CAM) is a high-speed lookup memory, which searches the entire memory in parallel and provides address of the input search word. Internet of things (IoT) technology needs access control list filters, deployed using CAM, to reduce the flow of invalid data through the network. Field-programmable gate arrays (FPGAs) play an important role to provide the computational power to IoT nodes using ultra low power modern devices. CAMs are emulated in FPGAs using different memories, i.e., block RAM, distributed RAM, and flip-flops (FFs). FPGA-based CAMs have large power consumption due to the involvement of each CAM cell in parallel comparison. This work presents a bank-selective strategy for gate-based binary CAM on FPGA, which reduces the amount of comparisons and reduces power consumption on target FPGA device. For every input search key, only one bank is activated using gated-clock to compare the input key to corresponding stored rules. A sample of 512 x 36 of the proposed architecture with four banks is implemented on Xilinx Virtex-6 FPGA that consumes 42% less dynamic power compared to the best available CAM designs. Hardware resources of the proposed CAM design on target FPGA is reduced in terms of slice registers (SRs) and lookup tables (LUTs) by 7.9% and 8.8%, respectively, compared with the latest prior work.

The universal software radio peripheral (USRP) is a versatile software defined radio (SDR) platform, developed by Ettus Research™, which is intended for a wide variety of applications ranging from communication links to RADAR. We have investigated another application of the USRP by implementing a transceiver capable of interrogating passive, wireless surface acoustic wave (SAW) sensors centered at 915MHz. Interrogation of wideband orthogonal frequency coded (OFC) SAW sensors imposes strict requirements on the timing and synchronization of the transceiver. In the standard mode of operation, samples are generated and streamed between the USRP and host computer, introducing latency and bandwidth limitations due to the sampling bus. To achieve the performance required for this application, the USRP FPGA has been modified to introduce new functionality. Extraction of the sensor temperature is accomplished with a custom matched filter correlator. The system is capable of interrogating multiple sensors and can quickly reconfigure the USRP. Demonstration of the USRP wireless sensor system is achieved by interrogating wireless SAW OFC sensors at 915MHz and extracting the sensor temperature.

Direction of Arrival (DOA) estimation is an important fundamental problem in wireless signal processing. The current research on DOA estimation is mainly carried out in the MATLAB software simulation environment, but there is a large difference between the pure software simulation and the actual results. In order to better study the practical application, this paper uses two Universal Software Radio Peripheral (USRP) as the hardware base, and combines the Simulink software platform to realize the ratio amplitude algorithm direction measurement. In the paper, the reasons and solutions for amplitude calibration as well as data synchronization in the system are firstly described, then the formula of the amplitude ratio algorithm is fitted by the measured data, and finally the DOA estimation system is implemented and tested by USRP and Simulink. The experimental results show that the system is capable of accomplishing the DOA estimation function, which provides a convenient and reliable experience for source angle estimation as well as signal processing researchers.

There is presently a high interest in the spatial industry to develop high-performance on-board processing platforms with a high degree of flexibility, so they can adapt to varying mission needs and/or to future space standards. For this purpose, Field Programmable Gate Array (FPGA) devices have demonstrated to offer an excellent compromise between flexibility and performance. This work presents a novel FPGA-based architecture to be used as part of the hyperspectral linear unmixing processing chain. In particular, this paper introduces a new architecture for hyperspectral endmember extraction accordingly to the Modified Vertex Component Analysis (MVCA) algorithm, which provides a better figure of merit in terms of endmember extraction accuracy versus computational complexity than the Vertex Component Analysis (VCA) algorithm. Two versions of the MVCA algorithm which differ on the use of floating point or integer arithmetic for iteratively projecting the hyperspectral cube onto a direction orthogonal to the subspace spanned by the endmembers already computed have been mapped onto a Xilinx Virtex-5 FPGA. The results demonstrate that both versions are capable of processing hyperspectral images captured by the NASA's AVIRIS sensor in real-time, showing the latter a better performance in terms of hardware resources and processing speed. Furthermore, our proposal constitutes the first published architecture for extracting the endmembers from a hyperspectral image based on the VCA principle and thus, it provides a basis for future FPGA implementations of state-of-the-art hyperspectral algorithms with similar characteristics, such as the Automatic Target Generation Process (ATGP) or the Orthogonal Subspace Projection (OSP) algorithms.

This work presents a multi-channel time-to-digital converter (TDC) based on a field-programmable gate array (FPGA). This TDC shares many advantages of custom circuitry but few of the drawbacks. A thorough characterization of the TDC, based on a Xilinx Virtex-6 FPGA, is presented and several performance parameters are described, including distortions due to the FPGA architecture, temperature effects, intra-chip position variation, and chip-to-chip variation. An optimized TDC exhibits 10ps resolution, 3.86LSB integral non-linearity, and a throughput of 300MS/s. Also, measurements are shown for TDC-to-TDC distortion for multi-channel TDCs and simulations are performed to investigate parallelism using multiple TDCs. Results imply that FPGA-based TDCs can achieve high performance, and can be used in a wide range of applications requiring high throughput and accurate time measurements.

Ternary content-addressable memories (TCAMs) are used to design high-speed search engines. TCAM is implemented on application-specific integrated circuit (native TCAMs) and field-programmable gate array (FPGA) (static random-access memory (SRAM)-based TCAMs) platforms but both have the drawback of high power consumption. This paper presents a pre-classifier-based architecture for an energy-efficient SRAM-based TCAM. The first classification stage divides the TCAM table into several sub-tables of balanced size. The second SRAM-based implementation stage maps each of the resultant TCAM sub-tables to a separate row of configured SRAM blocks in the architecture. The proposed architecture selectively activates at most one row of SRAM blocks for each incoming TCAM word. Compared with the existing SRAM-based TCAM designs on FPGAs, the proposed design consumes significantly reduced energy as it activates a part of SRAM memory used for lookup rather than the entire SRAM memory as in the previous schemes. We implemented the proposed approach sample designs of size 512 × 36 on Xilinx Virtex-6 FPGA. The experimental results showed that the proposed design achieved at least three times lower power consumption per performance than other SRAM-based TCAM architectures.

We propose a low complexity synchronization method for the 3rd Generation Partnership Project (3GPP) long term evolution (LTE) mobile communication systems. A low complexity detection window, synchronization state machine, and two-stage detection are used to lower the computational complexity. The positions of the detection window and received samples are recorded, and the position and length of the detection window are controlled by the state machine. The positions are compared to decide if the received sample is useful for synchronization signal detection. Such techniques avoid unnecessary computations especially when implementing a receiver on a software defined radio (SDR) platform with general-purpose processors. We analyze the computational complexity of the proposed method and evaluate its performance based on simulations and using a Universal Software Radio Peripheral (USRP)-based SDR platform. The evaluation shows that the proposed method provides reliable and real-time synchronization signals on the considered SDR platform.

This paper presents a hardware implementation of morphological operations based on dynamic and partial reconfiguration (DPR) technique. This technique allows reconfiguring a part of the FPGA area with different functionalities at runtime. It is a promising solution toincrease performance in the system. Our design allows todesigner to choose the adequate morphological operation (erosion or dilation) according the image constraints. We use xilinx tools and Virtex-5 FPGA board. To evaluate our implementation, we measure the performance in terms of area occupation and time reconfiguration. The results show the implementation of morphological operations on FPGA (Field Programmable Gate Array) using DPR can improve the performance and saving at least 11% of area.

Creating an environment of ldquono doubtrdquo for mission success is essential to most critical embedded applications. With reconfigurable devices such as field programmable gate arrays (FPGAs), designers are provided with a seductive tool to use as a basis for sophisticated but highly reliable platforms. We propose a two-level self-healing methodology for increasing the probability of success in critical missions. Our proposed system first undertakes healing at node-level. Failing to rectify system at node-level, network-level healing is undertaken. We have designed a system based on Xilinx Virtex-5 FPGAs and Cirronet DM2200 wireless mesh nodes to demonstrate autonomous wireless healing capability among networked node devices.

We investigate the use of the particle filtering sequential Bayesian estimation technique and its hardware implementation for tracking neural activity. We propose using the multiple particle filter (MPF) approach in order to reduce the computational intensity incurred due to the large number of sensors required to observe the noninvasive magnetoencephalography (MEG) measurements needed to estimate the brain current dipole source locations and moments when tracking neural activity. The improved tracking performance of the MPF is demonstrated using numerical simulations on synthetic and real data. We also investigate the parallel implementation of the MPF algorithm on a Xilinx Virtex-5 field-programmable gate array (FPGA) platform. Our results of significant reduction in timing requirements demonstrate that the implementation is suitable for real-time tracking.