FPGA-Based Multiple DDoS Countermeasure Mechanisms System Using Partial Dynamic Reconfiguration

We study the fundamental capacity trade-off between full-duplex and half-duplex transmission modes in a two- hop communication system with a fixed infrastructure-based amplify-and-forward relay. First, we derive closed-form expressions for the average end-to-end capacity in the relay link. We show that it may be better to tolerate some loop interference with the full-duplex mode than to consume channel resources by allocating two orthogonal channels with the half-duplex mode. Furthermore, we evaluate the maximum loop interference power levels that still allow the full-duplex mode to achieve the same capacity as the half-duplex mode. Our results indicate that with practical signal-to-noise ratio values, the full-duplex mode is preferable in terms of capacity.

This paper proposes a reconfigurable heterogeneous multicore architecture to integrate multiple DDoS defense mechanisms for DDoS protection. The architecture allows multiple cooperating DDoS mitigation techniques to classify incoming network packets. The proposed architecture consists of two separated partitions: static and dynamic. The static partition includes packet pre-processing and post-processing modules while the DDoS filtering techniques are implemented on the dynamic partition. These filtering techniques can be implemented by either hardware custom computing cores or general purpose soft processors or both. In all cases, these DDoS filtering computing cores can be updated or changed at runtime or design time. We implement our first prototype system with Hop-count filtering and Ingress/Engress filtering techniques using Xilinx Virtex 5xc5vtx240t FPGA device. The synthesis results show that the system can work at up to 116.782MHz while utilizing about 41% LUTs, 47% Registers, and 53% Block Memory of the available hardware resources. The system achieves the detection rate of 100% with the false negative rate at 0% and false positive rate closed to 0.74%. The prototype system achieves packet decoding throughput at 9.869 Gbps in half-duplex mode and 19.738 Gbps in full-duplex mode.

This paper proposes an FPGA-based multicore architecture to integrate multiple DDoS defense mechanisms for DDoS protection. The architecture allows multiple cooperating DDoS mitigation techniques to classify incoming network packets. The proposed architecture consists of two separate partitions static and dynamic. The static partition includes packet pre-processing and post-processing modules while the DDoS filtering techniques are implemented within the dynamic partition. These filtering techniques can be implemented by either hardware custom computing cores or general purpose soft processors or both. In all cases, these DDoS filtering computing cores can be updated or changed at runtime or design time. We implement our first prototype system with the Hop-count filtering and Ingress/Engress filtering techniques using the Xilinx Virtex 5 xc5vtx240t FPGA device. The synthesis results show that the system can work at up to 116.782MHz while utilizing about 41% LUTs, 47% Registers, and 53% Block Memory of the available hardware resources. Experimental results show that our system achieves a 100% detection rate (true positive) with a 0% false negative rate and the maximum 0.74% false positive rate. Moreover, the prototype system obtains packet processing throughput by up to 9.869 Gbps in half-duplex mode and 19.738 Gbps in full-duplex mode.

In this paper, we analyze the performance of underlay communication between full-duplex capable device-to-device (D2D) nodes transmitting in the cellular band. The D2D nodes use peak interference type of power control to restrict the overall interference at the cellular base station below a statistically determined interference temperature limit (ITL), thereby ensuring its quality of service for uplink cellular users. From the derived analytical expressions, sum-throughput optimal strategies are evolved to choose between full-duplex and half-duplex modes of operation for the D2D nodes. Since both D2D nodes transmit simultaneously in full-duplex mode, the ITL needs to be apportioned between the D2D terminals. A closed-form expression is presented for the optimum ITL apportioning that maximizes D2D sum-throughput. It is shown that switching to half-duplex mode is advantageous when the target rate is above a certain critical target-rate, for which an expression is derived. Computer simulations are presented that demonstrate accuracy of the derived expressions.

Hybrid duplex wireless networks, use half duplex (HD) as well as full duplex (FD) modes to utilize the advantages of both technologies. This paper tries to determine the proportion of the network nodes that should be in HD or FD modes in such networks, to maximize the overall throughput of all FD and HD nodes. Here, by assuming imperfect self-interference cancellation (SIC) and using ALOHA protocol, the local optimum densities of FD, HD and idle nodes are obtained in a given time slot, using Karush–Kuhn–Tucker (KKT) conditions as well as stochastic geometry tool. We also obtain the sub-optimal value of the signal-to-interference ratio (SIR) threshold constrained by fixed node densities, using the steepest descent method in order to maximize the network throughput. The results show that in such networks, the proposed hybrid duplex mode selection scheme improves the level of throughput. The results also indicate the effect of imperfect SIC on reducing the throughput. Moreover, it is demonstrated that by choosing an optimal SIR threshold for mode selection process, the achievable throughput in such networks can increase by around 5%.

Multi-antenna relay assisted NOMA network with multiple imperfect factors

Dynamic reconfiguration techniques can greatly improve the flexibility and reliability of manufacturing systems. However, different from static reconfigurable systems, system behavior during dynamic reconfiguration processes is quite complex due to possible concurrence of system structure changes and events inside unaltered components. This increases the difficulty in designing and developing dynamic reconfigurable systems. The current paper deals with the analysis and control of dynamic reconfiguration process of manufacturing systems from the perspective of discrete event systems. To this end, the authors improve the reconfigurable timed net condition/event systems formalism by assigning reconfiguration functions with extra permeating time, action ranges, and concurrent decision functions. As a consequence, nondeterministic behavior of a dynamic reconfigurable system during dynamic reconfigurations can be specified, while the system correctness, coherence, and safety during reconfigurations can be guaranteed. A reconfigurable manufacturing plant is used as a running example to illustrate the contribution of this paper.

In this paper we investigate the effect of interference caused by in-band full-duplex radios in device-to-device communication (D2D). While using full-duplex radios in D2D, both users transmit, compared to half-duplex D2D in which one user transmits. This is going to cause more interference in underlay D2D communication since D2D link operates on the same radio resource blocks as cellular users. We consider uplink radio resource reuse of cellular users by D2D communication, and try to maximize the number of possible D2D links constrained to the interference on the cellular user. The number of D2D pairs that can be active in the full-duplex mode is smaller than in the half-duplex mode due to more interference from transmissions of both D2D nodes. We compare the total rate of half-duplex and full-duplex modes and evaluate the benefits of full-duplex radios.

This article studies the energy efficiency (EE) of a three-node decode-and-forward (DF) relay channel, where the relay operates in full-duplex (FD) or half-duplex (HD) mode. In particular, for the FD mode, both the residual self-interference (RSI) and the extra circuit power consumption introduced by the self-interference cancellation (SIC) at the relay node are considered and modeled as linear functions over the relay transmission power. Under this setup, the EE maximization problems for the considered FD and HD modes subject to the total transmission power and spectral efficiency (SE) constraints are formulated as max–min problems, whose optimal power allocation is computed by fractional programming. Next, the EEs for the FD, HD, and direct transmission (DT) modes are compared under different channel conditions, and a hybrid mode selection scheme, i.e., selecting the one with the maximum EE among the above three modes, is proposed. Besides, we also prove that both the EE and the SE monotonically increase with the total transmission power under a given condition. Finally, numerical results show that the maximum EE of the FD relaying exceeds those of the HD and DT ones when the required SE is relatively high. Furthermore, the proposed hybrid mode selection scheme can provide up to 192.4% higher EE compared with the DT mode.

In order to realize a dynamic reconfiguration technique that automatically switches configurations and functions of an optical device, we need a technique to control freely the connections of light inside and between devices without needing submicron-level alignments. In this study, we investigate the behavior of dynamic index gratings with nanoscale reversible self-organization in Sn 2 P 2 S 6 crystals that we have newly developed so as to realize an autonomous and dynamic reconfigurable optical waveguide by externally controlling its motions with light and examine its basic properties. Experimental results showed autonomous and dynamic reconfigurations of the optical waveguide formed in a Sb doped Sn 2 P 2 S 6 crystal with a 4 mm thickness for variations of an incident light position. We have successfully reconfigured the waveguide by a self-organization based on a photorefractive effect without cutting time series signals flowing through the waveguide, for variations of an incident light position long as approximately 2000 μm. Furthermore, we have recognized tolerance up to around 0.2 degrees for incidence angles in the experiment. This technique allows us to connect light freely without needing spatial adjustments in a nanostructured optical waveguide seen in photonic crystal fibers. Moreover, it is a technique that can be applied to dynamic connections between optical fibers and integrated waveguides accompanied with time variations of spatial modes. We also verified a possibility of removable and replaceable optical connection by utilizing large shift-tolerance of the autonomous and dynamic reconfigurable waveguide.

The severe interference in full-duplex (FD) cellular network largely degrade the system performance, especially for cell edge users. In this paper, hybrid full/half duplex cellular network which is composed of a mixture of FD and half duplex (HD) base-stations (BSs) is focused. In order to relieve the received inter-cell interference, frequency reuse (FR) is applied. The adopted FR schemes include traditional full FR and two kinds of fractional FR (FFR) named Strict FFR (StFFR) and Soft FFR (SoFFR). Stochastic geometry is adopted to evaluate the system performance. Tractable results of the ergodic rate and coverage probability for different FR schemes are obtained. Through the numerical results, we can observe that full FR and StFFR schemes can improve the user coverage probability at the expense of system spectrum efficiency (SE). SoFFR can improve both the coverage probability and the system SE. The numerical results also show that if the residual Self-interference is not very strong, operating all the BSs in FD mode can achieve the best performance, otherwise, it is better to operate all the BSs in HD mode.

A multi-mode circuit implements the functionality of a limited number of circuits, called modes, of which at any given time only one needs to be realised. Using dynamic partial reconfiguration of an FPGA, all the modes can be implemented on the same reconfigurable region, requiring only an area that can contain the biggest mode. This can save considerable chip area. Conventional dynamic partial reconfiguration techniques generate a configuration for every mode separately. As a result, to switch between modes the complete reconfigurable region is rewritten, which often leads to long reconfiguration times. In this paper we give an overview of research we conducted to reduce this overhead of dynamic partial reconfiguration for multi-mode circuits. In this research we explored several joint optimization strategies at different stages of the tool flow.

Current power saving techniques have been focused on reducing the dynamic power consumption induced by switching activity in CMOS digital circuits. Among these techniques, we can cite the clock gating, dynamic voltage frequency scaling, adaptive voltage scaling, and multiple voltage thresholds. Recently, as transistor sizes get smaller, the leakage power consumption has become a non-negligible and dominating part of the total power consumption. Thus, it is essential to take care of this new constraint in order to design low-power embedded wireless communication systems. It's well known that there are a strong relationship between leakage power and die-temperature, so that the larger leakage power consumption is associated with the higher temperature. In this paper we give a detailed analysis of FPGA leakage power consumption based on die temperature measurement. Also, after discretizing the FPGA area into several rectangular regions, we investigate whether dynamic partial reconfiguration technique can be performed over different regions to decrease average die-temperature, and consequently the leakage power consumption.

Dynamic partial reconfiguration technique can be used to modify regions of an FPGA as large as the whole reconfigurable fabric or as small as individual logic elements. However, FPGA manufacturers have focused their efforts on designing tools that support the design of monolithic reconfigurable accelerators spanning large regions of the device. Nevertheless, in some applications, it is enough to fine-tune the accelerators' behavior instead of changing them entirely. In these cases, rather than allocating new accelerators, it is possible to reconfigure individual logic elements of the circuit, such as look-up tables or flip-flops. There is also an intermediate approach that targets the reconfigurability of accelerators composed of several tightly interconnected modules, such as overlays. In those architectures, it is possible to reconfigure only the modules that differ between the existing accelerator versions, thus reducing the reconfigurable footprint granularity. This article proposes a classification of the approaches above, categorizing them as coarse, fine, and medium grain, respectively. There are neither commercial nor academic tools supporting multi-grain reconfiguration to take advantage of each granularity strength on commercial FPGAs. Differently, this article proposes a tool called IMPRESS, that provides design-time and run-time support for multi-grain reconfiguration in Xilinx 7 Series FPGAs. Specific criteria are provided to combine the different granularity levels, trading off the benefits in terms of flexibility and performance, with different design and run-time costs. Two use cases in the image processing and neural network domains have been implemented to show how IMPRESS can build multi-grain reconfigurable systems.

Full-duplex (FD) radio has been introduced for bidirectional communications on the same temporal and spectral resources so as to maximize spectral efficiency. In this paper, motivated by the recent advances in FD radios, we provide a foundation for downlink hybrid-duplex heterogeneous networks (HDHNs), composed of multi-tier networks with a mixture of access points (APs) operating either in FD mode or half-duplex (HD) mode. Specifically, we characterize the network interference from FD-mode cells, and derive the HDHN throughput by accounting for AP spatial density, self-interference cancellation (IC) capability, and transmission power of APs and users. By quantifying the HDHN throughput, we present the effect of network parameters and the self-IC capability on the HDHN throughput, which shows the superiority of FD mode for larger AP densities (i.e., larger network interference and shorter communication distance) or higher self-IC capability.