FPGA implementation of an LMS-based real-time adaptive Predistorter for Power Amplifiers

Abstract

Translate Article

This paper presents an adaptive Digital Predistorter (DPD) for Power Amplifier (PA) linearization whose implementation and real time adaptation have been fully performed in a Field Programmable Gate Array (FPGA) device responsible for the co-processing tasks. The predistortion function is carried out in a Basic Predistortion Cell (BPC) containing a Look-up Table (LUT). One of the main advantages of this DPD configuration is that adaptation is performed in a hot manner and therefore, it is not necessary to switch the DPD into a training mode in order to estimate the LUT contents. Results showing the linearization capabilities of this adaptive DPD are here provided.