From Control Design to FPGA Implementation

Building the machines that advance scientific knowledge is one of the most significant challenges of our time. So-called Big Science instruments are unique; the expertise required to build them is multidisciplinary, and few countries can build and maintain them. Since resources and budgets are not unlimited, these require efficient solutions. Big Science machines take a decade to plan, a decade to build, and at least a decade to operate. One such machine is the largest fusion reactor project, ITER, which promises to be the next step in fusion research and has a big challenge in system integration. To mitigate the integration effort, ITER has invested in standardization, both in software and hardware, introducing standard instrumentation software named Nominal Device Support (NDSv3); Micro Telecommunication Computing Architecture (MTCA) as the long-term hardware standard choice, and EPICS as a general-purpose distributed control system. These control systems are essential in the management of the facility. They provide functions such as communication protocols, process management, monitoring, alarms, and human-machine interfaces. But also, more advanced access to databases or data acquisition systems. The latter is typically managed by a Field Programmable Gate Array (FPGA), of which facilities can easily have thousands of these FPGAs managing millions of signals within the control system environment. Nevertheless, these FPGA data acquisition (DAQ) systems continue to be labor-intensive. Standardized, modular, and open-source frameworks have been proposed to solve this problem, however, the FPGA programming expertise requirement remained. This thesis proposes a complete technology stack that considers these DAQ systems from the control system to the hardware. It provides a methodology using the Open Computing Language (OpenCL) to reduce the FPGA programming effort. The FPGA devices are programmed using C/C++-like environments, which are much simpler than traditional Hardware Description Languages (HDLs). The software, named IRIO-OpenCL, is written in C++ following ITER's NDSv3 model, which abstracts and generalizes the development of software device drivers and simplifies the interface to EPICS. IRIO-OpenCL is specifically designed to simplify the integration of intelligent instrumentation systems, allowing the integration of algorithms into the FPGA without modifying large parts of the supporting library. The MTCA standard was chosen to maintain modularity. The chassis backplane connects to the devices via Ethernet and PCIe, enabling standard communications. The Advanced Mezzanine Card is the typical MTCA FPGA-based DAQ carrier board. It connects the FPGA to the chassis backplane and typically provides FPGA Mezzanine Connectors (FMCs) for plugging in analog-to-digital (ADC) carrier boards. An ADC connected via the FMC interface samples the analog signals passed to the OpenCL processing kernels. Using OpenCL, the FPGA kernels communicate with the host machine in a standardized way. To demonstrate the applicability of this methodology, reference problems were selected from the literature and implemented, both with traditional and deep learning (DL) solutions. The methodology elaborates on connecting the OpenCL kernels for any use case, and the results show examples of kernel sets. The neutron flux measurement problem is solved at 1GS/s in real time using pulse counting and Campbell techniques, using 40% of the target Arria10 FPGA. The DL application example is based on a neutron/gamma discrimination neural network (NN) that achieves a classification rate of up to 1.3 MEvents/s using less than 25% of the target resource. RESUMEN Construir máquinas que avancen el conocimiento científico es uno de los desafíos más significativos de nuestro tiempo. Los instrumentos de la llamada Big Science son únicos; las competencias requeridas para su construcción son multidisciplinares, y pocos países pueden construirlos y mantenerlos. Dado que los recursos y presupuestos no son ilimitados, estos requieren soluciones eficientes. Las máquinas de Gran Ciencia tardan una década en planificarse, una década en construirse y al menos una década en operarse. Una de estas máquinas es el proyecto del reactor de fusión más grande, ITER, que promete ser el siguiente paso en la investigación de fusión y presenta un gran desafío en la integración de sistemas. Para mitigar el esfuerzo de integración, ITER ha invertido en estandarización, tanto en software como en hardware, introduciendo un software de instrumentación estándar llamado Nominal Device Support v3 (NDSv3); Micro Telecommunication Computing Architecture (MTCA) como la elección estándar de hardware a largo plazo, y EPICS como un sistema de control distribuido de propósito general. Estos sistemas de control son esenciales en la gestión de la instalación ya que proporcionan funciones como protocolos de comunicación, gestión de procesos, monitorización, alarmas e interfaces de usuario, además de acceso avanzado a bases de datos o sistemas de adquisición de datos. Este último es típicamente gestionado por un Field Programmable Gate Array (FPGA), de los cuales las instalaciones pueden tener fácilmente miles de unidades gestionando millones de señales dentro del entorno del sistema de control. Estos sistemas de adquisición de datos (DAQ) con FPGA siguen requiriendo programación experta y laboriosa. Se han propuesto marcos estandarizados, modulares y de código abierto para resolver este problema, sin embargo, la necesidad de experiencia en programación FPGA no se ha podido eludir. Esta tesis propone una pila de tecnologías que considera estos sistemas DAQ desde el sistema de control hasta el hardware. Proporciona una metodología utilizando el Open Computing Language (OpenCL) para reducir el esfuerzo de programación FPGA. Los dispositivos FPGA se programan utilizando entornos similares a C/C++, que son mucho más simples que los Lenguajes de Descripción de Hardware (HDL) tradicionales. El software, llamado IRIO-OpenCL, está escrito en C++ siguiendo el modelo de NDSv3 de ITER, que abstrae y generaliza el desarrollo de controladores de dispositivos de software y simplifica la interfaz con EPICS. IRIO-OpenCL está específicamente diseñado para simplificar la integración de sistemas de instrumentación inteligentes, permitiendo la integración de algoritmos en el FPGA sin modificar grandes partes de la biblioteca de soporte. El estándar MTCA fue elegido para mantener la modularidad. El backplane del chasis se conecta a los dispositivos a través de Ethernet y PCIe, habilitando comunicaciones estándar. La Advanced Mezzanine Card es la placa portadora DAQ FPGA típica de MTCA, que conecta el FPGA al backplane del chasis y típicamente proporciona FPGA Mezzanine Connectors (FMC) para conectar placas con conversores analógico-digitales (ADC). Un ADC conectado a través de la interfaz FMC muestrea las señales analógicas pasadas a los núcleos de procesamiento OpenCL. Utilizando OpenCL, los núcleos FPGA se comunican con la máquina anfitriona de una manera estandarizada. Para demostrar la aplicabilidad de esta metodología, se seleccionaron e implementaron problemas de referencia de la literatura, tanto con soluciones tradicionales como de Deep Learning (DL). La metodología elabora ejemplos de conexión de núcleos OpenCL para cualquier caso de uso, y los resultados muestran ejemplos de conjuntos de núcleos. El problema de medición del flujo de neutrones se resuelve a 1GS/s en tiempo real utilizando técnicas de conteo de pulsos y Campbell, utilizando el 40% del objetivo FPGA Arria10. El ejemplo de aplicación DL se basa en una red neuronal para la discriminación neutrones/gammas que logra una tasa de clasificación de hasta 1.3 MEventos/s utilizando menos del 25% de la FPGA objetivo. LABURPENA Ezagutza zientifikoa aurreratzen duten makinak eraikitzea gure garaiko erronka garrantzitsuenetako bat da. Big Science deritzonaren makinak bakarrak dira; beharrezko esperientzia diziplina anitzekoa da, eta herrialde gutxik eraiki eta mantendu ditzakete. Baliabideak eta aurrekontuak mugagabeak ez direnez, konponbide eraginkorrak behar dira. Zientzia Handi makinak hamarkada bat behar dute diseinatuak izateko, hamarkada bat eraikitzeko eta gutxienez hamarkada bat jarduteko. Makina horietako bat fusio-erreaktore handienaren proiektua da, ITER, fusio-ikerketan hurrengo urratsa izango dena eta sistemak integratzeko erronka handia aurkezten duena. Integrazio-ahalegina arintzeko, ITERek estandarizazioan inbertitu du, bai softwarean bai - eta EPICS helburu orokorreko kontrol-sistema banatua. Kontrol-sistema horiek funtsezkoak dira instalazioa kudeatzeko. Komunikazio-protokoloak, prozesuen kudeaketa, monitorizazioa, alarmak eta pertsona-makina interfazeak bezalako funtzioak ematen dituzte, datubaseetarako edo datuak eskuratzeko sistemetarako sarbide aurreratua izateaz gain. Azken hori "Field Programmable Gate Array" (FPGA) batek kudeatzen du, milaka FPGA konektatuz makina bakoitzean eta kontrol-sistemaz milioika seinale kudeatuz. FPGA duten datuak eskuratzeko sistemek (DAQ) programazio aditua eta neketsua eskatzen jarraitzen dute. Problema hori ebazteko marko estandarizatuak, modularrak eta kode irekikoak proposatu dira, hala ere, FPGA hardware programazio espezializatuaren beharra ezin izan da ukatu. Tesi honek DAQ sistema hauek kontrol sistematik hardwareraino kontsideratuz teknologia bilduma bat programazio-ahalegina murrizten du. FPGA gailuak C/C++ antzeko inguruneak erabiliz programatzen dira, - OpenCL izenekoa, C++n idatzita dago, ITERren "Nominal Device Support v3" (NDSv3) eredua jarraituz. Honek software-gailuen garapena diseinu abstraktu eta orokorrez EPICSekiko interfazea sinplifikatzen du. IRIOOpenCL berariaz diseinatuta dago instrumentazio-sistema adimendunen integrazioa sinplifikatzeko, eta algoritmoak FPGAn integratzea ahalbidetzen du, software zati handiak aldatu gabe. Modularitateari eusteko, MTCA estandarra aukeratu da. Txasisaren backplanea Ethernet eta PCIe bidez konektatzen da gailuetara, komunikazio estandarrak gaituz. "Advanced Mezzanine Card" MTCAren ohiko DAQ FPGA plaka eramailea da. FPGA txasisaren backplanera konektatzen du eta, normalean, "FPGA Mezzanine Connectors"ak (FMC) ditu plaka bihurgailu analogiko-digitalak (ADC) konektatzeko. ADCak, FMC interfazearen bidez konektatuta, OpenCL prozesatze-nukleoetara igarotako seinale analogikoak bihurtzen ditu. OpenCL erabiliz, FPGA nukleoak ordenagailuarekin modu estandarizatuan komunikatzen dira. Metodologia horren aplikagarritasuna egiaztatzeko, erreferentziazko adibideak literaturatik hautatu eta nukleoen konexio-adibideak egiten ditu, edozein kasutan erabiltzeko, eta emaitzek nukleo multzoen adibideak erakusten dituzte. Neutroi-fluxuaren neurketak 1GS/s-ko ebazten dira real time errendimenduaz, pultsuak eta Campbell zenbatzeko teknikak erabiliz, Arria10 FPGAren % 40 erabiliz. Azkenik, DL aplikazioaren adibidea, neutroi/gamma sailkapena, sare neuronal batean oinarritzen da, eta FPGAren baliabideen % 25 baino gutxiago erabiliz 1.3 MSailkapen/s sailkapen-tasa lortzen du.

New Mechatronics Development Techniques for FPGA-Based Control and Simulation of Electromechanical Systems

In this paper, we describe the multiple biometric recognition system based on 32 bit floating-point digital signal processor (DSP) and field programmable gates array (FPGA). In addition, it has the function of real-time display, which can help the users easily capture the perfect image that they need. Different from other platforms of using DSP and FPGA, we have two kinds of parallel bus interfaces between them, the EMIF and HPI interface. With the help of the Hardware Description Language (HDL) Verilog HDL, we make it true that the DPS and FPGA can co-process the matching algorithms. Comparing with the matching time that processes only by the DSP, the co-processing is more efficient than the processing only by one processor. Besides, we leave several parallel and series interfaces in our board for the future use. Therefore, our system can be applied to many different digital signal processing domains and provide them an excellent computing platform.

Nowadays the need for dealing with ultra-high speed Analog to Digital Converter (ADC) is becoming more and more common, from Telecommunications to Precise Instrumentation, every application is increasing the analog to digital interface data rate. The ultra-high sampling rate of the ADCs demands the use of advanced acquisition techniques as well as the latest technology available. The utilization of dedicated Application Specific Integrated Circuit (ASIC) is an expensive solution to deal with the very high throughput from the ADC and its lack of flexibility is a huge drawback. On the other hand, the technology, the architecture and the state-of-the art of the current Field Programmable Gate Arrays (FPGAs) make them especially suitable to act as interface between an ultra-high speed ADC and a data processing unit. Another extra advantage is the reconfigurability of the FPGAs, they can be quickly adapted to different ADCs or different data processing units. The purpose of this paper is to present a practical approach to interface an ultra-high speed 8-bit ADC, MAX104, from Maxim Integrated Circuit, which performs digitalization of the input signal with a sampling rate of 1Gsps and a commercial and popular FPGA, the Virtex2 Pro, from Xilinx Corporation. Once the ADC digital data have been acquired, then they can be processed by either the dedicated FPGA Digital Signal Processing (DSP) blocks, or the FPGA embedded processors or just send the data out to a PC for later processing. Hence, the proposed method of implementation can be used as front-end of a wide range of applications.

Motion estimation in videos is a computationally intensive process. A popular strategy for dealing with such a high processing load is to accelerate algorithms with dedicated hardware such as graphic processor units (GPU), field programmable gate arrays (FPGA), and digital signal processors (DSP). Previous approaches addressed the problem using accelerators together with a general purpose processor, such as acorn RISC machines (ARM). In this work, we present a co-processing architecture using FPGA and DSP. A portable platform for motion estimation based on sparse feature point detection and tracking is developed for real-time embedded systems and smart video sensors applications. A Harris corner detection IP core is designed with a customized fine grain pipeline on a Virtex-4 FPGA. The detected feature points are then tracked using the Lucas---Kanade algorithm in a DSP that acts as a co-processor for the FPGA. The hybrid system offers a throughput of 160 frames per second (fps) for VGA image resolution. We have also tested the benefits of our proposed solution (FPGA + DSP) in comparison with two other traditional architectures and co-processing strategies: hybrid ARM + DSP and DSP only. The proposed FPGA + DSP system offers a speedup of about 20 times and 3 times over ARM + DSP and DSP only configurations, respectively. A comparison of the Harris feature detection algorithm performance between different embedded processors (DSP, ARM, and FPGA) reveals that the DSP offers the best performance when scaling up from QVGA to VGA resolutions.

Measurements of radiation effects in an antifuse FPGA

Editorial

This paper presents the simulation study of nonlinear dynamic of cardiac excitation based on Luo Rudy Phase I (LR-I) model towards numerical solutions of ordinary differential equations (ODEs) responsible for cardiac excitation on field programmable gate arrays (FPGAs). As computational modeling needs vast of simulation time, a real-time hardware implementation using FPGA could be the solution as it provides high configurability and performance. For rapid prototyping, MATLAB Simulink that offers a link with the FPGA has been used. Through Simulink HDL Coder, a tool in the MATLAB software that capable to convert the MATLAB Simulink blocks into hardware description language (HDL) code and an FPGA-in-the-loop (FIL) and co-simulation for verification, FPGA hardware implementation can be done. As a result, the LR-I excitation model is successfully simulated by using the MATLAB Simulink and the VHDL code has been successfully generated by the HDL Coder after fixed-point optimization is done. The FIL verification on actual FPGA board also has shown quantitatively comparable results to the MATLAB Simulink simulation. Therefore, the design flow has given a positive outlook in developing this FPGA stand-alone implementation.

Reconfigurable hardware, such as Field Programmable Gate Arrays (FPGAs), are being increasingly deployed in diverse application areas including automotive systems, critical infrastructures, and the emerging Internet of Things (IoT), to implement customized designs. However, securing FPGA-based designs against piracy, reverse engineering, and tampering is challenging, especially for systems that require remote upgrade. In many cases, existing solutions based on bit-stream encryption may not provide sufficient protection against these attacks. In this paper, we present a novel obfuscation approach for provably robust protection of FPGA bitstreams at low overhead that goes well beyond the protection offered by bitstream encryption. The approach works with existing FPGA architectures and synthesis flows, and can be used with encryption techniques, or by itself for power and area-constrained systems. It leverages “FPGA dark silicon” — unused resources within the configurable logic blocks — to efficiently obfuscate the true functionality. We provide a detailed threat model and security analysis for the approach. We have developed a complete application mapping framework that integrates with the Altera Quartus II software. Using this CAD framework, we achieve provably strong security against all major attacks on FPGA bitstreams with an average 13% latency and 2% total power overhead for a set of benchmark circuits, as well as several large-scale open-source IP blocks on commercial FPGA.

Space based systems are looking more and more to the benefits from high performance, reconfigurable computing systems and Commercial Of The Shelf components (COTS). One critical reliability concern is the behaviour of the complex integrated circuits in a radiation environment. Field programmable gate arrays (FPGAs) are well suited for the small volumes in space applications. This type of products are driven by the commercial sector, so devices intended for the space environment must be adapted from commercial product. Heavy ion characterisation has been performed on several FPGA types and technologies to evaluate the onorbit radiation performance. As the geometry keeps shrinking, the relative importance of various radiation effects may change. Investigation of radiation effects on each technology generation is found to be necessary. This paper presents methodologies and results of radiation tests performed on commercial FPGA s for space applications. Mitigation of Single Event Upsets will be discussed.

The book focuses on the cost/area, performance and power consumption differences between Field-Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs). These differences are referred to as the gap between FPGAs and ASICs and knowledge of this gap is fundamental for people who design FPGAs, who use FPGAs, or who are considering their use. This book reviews and examines the gap in two ways. The first portion of the book focuses on measurements of the silicon area, performance, and power consumption gap. This is done by comparing designs implemented on a commercial FPGA and using an ASIC methodology. Through this comparison, various trends are noted to elucidate some of the design choices that can narrow the gap. The latter half of the book focuses on the trade-offs that can be made in the creation of a FPGA to narrow the gap selectively. This is useful because silicon area, performance and power consumption are not equally important to all users of FPGAs. The book describes the approach used to investigate these trade-offs and it includes a detailed description of the transistor sizing tool developed to assist in this investigation. The scope of the trade-offs is then examined and the effect of these trade-offs on the FPGA to ASIC gap is considered. The idea of making cost and performance trade-offs has been considered in past works but this book explores the use of transistor-sizing to enable these trade-offs.

The advent of space applications with increased computational requirements has led the space industry to consider innovative chips and avionics architectures for high-performance on-board data processing. In a relatively limited market, the European BRAVE family of Field-Programmable Gate Arrays (FPGAs) offers such novel radiation-hardened solutions. Towards verification, the current work devises and applies a methodology to thoroughly assess the BRAVE FPGAs and their SW tools. The paper focuses on NG-Large, i.e., the largest FPGA of the 65nm Radiation-Hardened-By-Design (RHBD) technology of NanoXplore to date. The proposed approach comprises a number of customized steps to systematically evaluate the entire FPGA design flow. Initially, we carefully select and tune a set of high-performance Digital Signal Processing (DSP) & Computer Vision (CV) benchmarks, which were originally developed as Hardware Description Language (HDL) IPs in past projects of the European Space Agency (ESA). Subsequently, we perform exhaustive exploration of the Synthesis, Placement, and Routing stages of the SW tools, as well as testing on actual HW boards. At each step, we generate and analyze a variety of results, while we also compare them to 3rd-party solutions. The results show that NG-Large provides sufficient programmability and performance, e.g., classic CV IPs for feature detection on megapixel images can achieve a throughput of 5–10 frames per second, while the on-chip memory utilization is up to 56% better than that of 3rd-party FPGAs. As a highlight, at system-level, we successfully implement and execute an entire HW/SW algorithmic pipeline for Vision-Based Navigation (VBN) involving SpaceWire data transfers with LEON CPU & NG-Large co-processing.

From edge devices to cloud servers, providing optimized hardware acceleration for specific applications has become a key approach to improve the efficiency of computer systems. Traditionally, many systems employ commercial field-programmable gate arrays (FPGAs) to implement dedicated hardware accelerator as the CPU's co-processor. However, commercial FPGAs are designed in generic architectures and are provided in the form of discrete chips, which makes it difficult to meet increasingly diversified market needs, such as balancing reconfigurable hardware resources for a specific application, or to be integrated into a customer's system-on-a-chip (SoC) in the form of embedded FPGA (eFPGA). In this paper, we propose an eFPGA generation suite with customizable architecture and integrated development environment (IDE), which covers the entire eFPGA design generation, testing, and utilization stages. For the eFPGA design generation, our intellectual property (IP) generation flow can explore the optimal logic cell, routing, and array structures for given target applications. For the testability, we employ a previously proposed shipping test method that is 100% accurate at detecting all stuck-at faults in the entire FPGA-IP. In addition, we propose a user-friendly and customizable Web-based IDE framework for the generated eFPGA based on the NODE-RED development framework. In the case study, we show an eFPGA architecture exploration example for a differential privacy encryption application using the proposed suite. Then we show the implementation and evaluation of the eFPGA prototype with a 55nm test element group chip design.

In this paper, we propose a hardware-enhanced mining framework to cope with many challenging data mining tasks in a data stream environment. In this framework, hardware enhancements are implemented in commercial Field Programmable Gate Array (FPGA) devices, which have been growing rapidly in terms of density and speed. By exploiting the parallelism in hardware, many data mining primitive subtasks can be executed with high throughput, thus increasing the performance of the overall data mining tasks. Simple operations like counting, which take a major portion of conventional mining execution time, can in fact be executed on the hardware enhancements very efficiently. Subtask modules that are used repetitively can also be replaced with the equivalent hardware enhancements. Specifically, we realize an Apriori-like algorithm with our proposed hardware-enhanced mining framework to mine frequent temporal patterns from data streams. The frequent counts of 1-itemsets and 2-itemsets are obtained after one pass of scanning the datasets with our hardware implementation. It is empirically shown that the hardware enhancements provide the scalability by mapping the high complexity operations such as subset itemsets counting to the hardware. Our approach achieve considerably higher throughput than traditional database architectures with pure software implementation. With fast increase in applications of mobile devices where power consumption is a concern and complicated software executions are prohibited, it is envisioned that hardware enhanced mining is an important direction to explore.

The motivation for single event effects (SEE) analysis and mitigation as part of the process for adaptation of a commercial Field Programmable Gate Array (FPGA) architecture for space-qualified applications is discussed. The interdependent roles of heavy-ion and laser-induced upset evaluation coupled with computer-aided investigations of SEE mechanisms and mitigation techniques in this process are shown to enable a significant reduction in SEE sensitivity of the device, while achieving minimal impact on remanufacturing steps.