GaAs PHEMT CHIP SETS AND IC PROCESSES FOR HIGH-END FIBER OPTIC APPLICATIONS

Optical interconnects for system-in-package applications can be designed for various bit rates. In this paper, an optimization study is conducted to find the optimal parameters for electrooptical links, based on a silicon photonic technology. We focus on the bit rate to achieve highest possible power efficiencies. This paper takes all the elements of an electrooptical link into account: serialization stage, ring-resonator-based modulator, thermal stabilization, modulator driver, laser, receiver, deserialization stage, and clock-phase generation. The optimization is based on a simulation-supported database for single-ended transimpedance amplifiers (TIAs). For all the other, elements of the link simulation-based power consumption models are presented. Furthermore, an analytical solution for the TIA bandwidth and bit rate relationship is derived based on the system jitter, the TIA noise, transimpedance, bandwidth and minimal output swing, and the available input signal. Optimal bit rates are derived and discussed for a 65-nm CMOS and a 28-nm fully depleted silicon-on-insulator technology. We found that the optimal bit rates increase with more aggressive technology scaling and smaller photodiode capacitances, but decrease if lower static power consumptions can be achieved (e.g., by efficient thermal tuning of ring-resonator modulators). We conclude that further research should aim for lower tuning powers instead of higher speed.

Rapid progress in multimedia communication requires large capacity optical transmission lines over 10 Gbit/s. One of the candidates considered for forthcoming high speed transmission systems is 20 Gb/s optical IM-DD transmission system. There have been several reports about IM-DD optical transmission experiments at 20 Gbit/s (1, 2, 3, 4). Monolithic integrated circuits are indispensable to turn such high speed optical transmission systems into practical application. The performance of various monolithic ICs for optical communications is summarized in Fig. 1. Si ICs are very attractive for realizing the high speed IM-DD systems up to 20 Gbit/s, because of their high uniformity and yield (5, 6, 7). The Si bipolar transistors, however, are not suited to fabricate circuits with high output voltage swing such as modulator driver, because of their breakdown voltage limitation. The compound devices, such as GaAs-HBTs, GaAs-MESFET and heterojunction FETs, have high cut-off frequency over 100 GHz (8, 9), so they are very effective to achieve the high speed ICs operating over 20 Gbit/s. They also have the advantage of utilizing microwave circuit technologies, which make it possible to design high frequency narrowband circuit, such as a clock amplifier at over 20 GHz.

The JCSAT 9 Communications Satellite, developed by Lockheed Martin Commercial Space Systems using an A2100 [1] spacecraft, will use an on-orbit configurable Frequency Generation Unit (FGU) that is SEU hard and total dose tolerant. The spacecraft is due for launch in 2005. The FGU design [2] illustrates the principles and benefits of a single loop synthesizer generating low noise and multiple local oscillators for various frequency (up/down) converters in the payload. Nineteen phase-locked loops are configured to provide coherent, multiple, and redundant C and L band local oscillator frequencies by combining digital, analog and microwave concepts to achieve small size, low mass, low DC power consumption, low phase noise, and spectral purity.

This letter presents the design and fabrication of a Ku-band resonant tunneling diode (RTD)-based quadrature voltage-controlled oscillator (QVCO) with low dc power consumption and good phase noise characteristics using an InP-based RTD/HBT MMIC technology. In order to achieve a low power operation, an InP-based RTD is used for microwave quadrature signal generation based on an excellent inherent negative differential resistance (NDR) characteristic of the RTD achieved at a low applied voltage. The fabricated QVCO core shows a low dc power consumption of 1.46 mW with excellent phase noise of -121.14 dBc/Hz at a 1 MHz frequency offset. The obtained figure-of-merit (FOM) is -202.8 dBc/Hz at an oscillation frequency of 14.6 GHz, which is one of the best values among Ku-band quadrature VCOs reported up to date.

A 2.5 Gbps transimpedance amplifier (TIA) with the feedback resistance self-adaptively adjusted is designed for the application of optical receivers in passive optical network and implemented in Global Foundries (GF) 0.18 [Formula: see text]m CMOS standard process. The main structure of the circuit consists of an improved three-stage current multiplexing push-pull inverter. With the diode-connected-transistor placed at each end of the inverter, the extra pole will be pulled away in order to increase the stability of the loop system. The feedback resistance of TIA is connected in parallel with the NMOS transistor, and the gate voltage of the tube is adjusted automatically to control the resistance value of this parallel structure in order to overcome the defect of the inverter which will work in the linear region on the condition of excessive optical power. A low-dropout linear regulator (LDO) is adopted from the power supply to the TIA to isolate power supply noise. The measured results demonstrate that the fabricated TIA with a photodetector capacitance of 3.2 pF has a transimpedance gain of 41.64 dB[Formula: see text] with a current signal frequency of 2.5 Gbit/s, and a −3 dB bandwidth of 2.35 GHz. The average input-referred noise current spectral density within the bandwidth is185 pA/Hz[Formula: see text], signal rise time is 195 ps, fall time is 227 ps, eye diagram height is 28 mV, optical sensitivity is −30.6 dBm, and power consumption is only 52 mW at 3.3 V power supply voltage, the chip area is [Formula: see text] mm2.

A W-band sub-harmonically injection-locked quadrature oscillator is proposed using 90-nm CMOS process in this paper. Based on a stacked boosting technique, the negative resistance of the oscillation core can be highly enhanced. The fundamental oscillation frequency of the proposed quadrature oscillator can be up to 104 GHz with a dc power consumption of 8.5 mW. A transformer coupling is employed to widen the locking range for the sub-harmonically injection-locked operation. With a sub-harmonic number of 3, the measured overall locking range is from 100 to 110 GHz. The measured phase noise at 10 kHz offset is lower than -82 dBc/Hz over the frequency. Compared to the prior art, this work features wide locking range, quadrature outputs, low dc power consumption, and high frequency.

The DC and RF performances of 40 nm high electron mobility transistors (HEMTs) with composite channel of InAs channel and In0.53Ga0.47As sub-channel were demonstrated. The drain current was 870 mA/mm (Vds=0.4V, Vgs=0V) and maximum gm was 1750 mS/mm (Vds=0.5V, Vgs=-0.65V). The devices showed high current gain cutoff frequency (fT) of 420 GHz and low gate delay time of 0.77 ps owing to the nanometer gate length and extremely high electron mobility of the InAs channel. Under low DC power consumption; these InAs HEMTs still exhibited excellent RF and logic performance which indicates these devices have great potential for future high-speed and low-voltage applications.

This paper presents a 190-GHz direct-conversion receiver capable of supporting higher-order modulation schemes and implemented in a SiGe BiCMOS technology. The circuit consists of a low-noise amplifier, an active fundamental mixer, a LO driver, a variable-gain baseband amplifier and a totem-pole output stage. To exploit the advantages of sub-THz frequencies in terms of available bandwidth at a low DC power consumption, all circuit blocks are concurrently optimized for large bandwidth and high power-efficiency. While consuming only 122 mW of DC power, the fabricated circuit exhibits a record 3-dB RF bandwidth of 35 GHz, a maximum conversion gain of 47 dB, a maximum baseband voltage swing of more than 800 mVpp and a minimum double-sideband noise figure of 10.7 dB.

Nitrogen-polar gallium nitride deep recess high electron mobility transistors have recently demonstrated exceptional mm-wave power density and efficiency when measured at 30 and 94 GHz. In addition to power and efficiency, linear operation with low DC power consumption is important because nonlinearities generate distortion and interference in both transmitters and receivers. This work presents the first measurements and analysis of the OIP3 and OIP3/P DC for an N-polar GaN deep recess device. An OIP3/P DC of up to 11.4 dB is demonstrated at 30 GHz using a vector receiver load pull system, and the linearity studied as a function of the bias current density.

In this paper, a W-band quadrature voltage-controlled oscillator (QVCO) with an injection-locked frequency divider (ILFD) is presented using 40-nm CMOS process. The QVCO is designed using a modified self-injection topology to minimize the quadrature error and phase noise. The injection-locked technique is employed in the frequency divider to achieve high frequency with low dc power consumption, and the division ratio is 3. The measured tuning range of the QVCO is from 93.3 to 97.4 GHz with a single-end output power of higher than -24 dBm. The measured average free-running phase noise of the QVCO is -80 dBc/Hz at 1-MHz offset. The overall dc power consumption of the QVCO and ILFD is 43 mW. The presented circuits are suitable for the phase-locked loop frontend.

Details of the design, fabrication, and measured data for an InGaAs high electron mobility transistor (HEMT) decade-bandwidth distributed coplanar waveguide (CPW) amplifier are presented. Comparison to a similar microstrip design is made. The design methodology highlights described here include CPW transmission line loss modeling. The circuit features the best reported CPW distributed amplifier noise figure and phase performance over 2-20 GHz as well as an on-chip bias network and low dc power consumption. The minimum measured noise figure is 2.1 dB with 11 dB maximum gain. The measured phase linearity is less than +or-50 over 2-20 GHz which makes this circuit well suited for system phased array applications where phase matching and linearity are a primary concern. >

In this paper, a Q-band balanced low noise amplifier (LNA) for radio astronomy applications is presented using 0.15-μm InGaAs metamorphic high electron mobility transistor (MHEMT) process. By using the balanced configuration, the input/output return losses and output 1-dB compression point of the LNA are improved. For the on-wafer measurement, the balanced LNA exhibits a broad bandwidth of from 27.3 to 50.7 GHz with a small-signal gain of 23.1 dB. The balanced LNA is further assembled in a packaged module for the cryogenic measurement. At a cryogenic temperature of 28 K, the average small-signal gain is higher than 19.5 dB from 30 to 50 GHz with the minimum equivalent noise temperature of 44.8 K. The proposed balanced LNA exhibits potential for radio astronomy applications due to its high small-signal gain, low noise, and low dc power consumption.

This paper reports approaches for reducing the power consumption for a passive switching mixer first receiver that are demonstrated in a 200-GHz low-IF (3.75 GHz) BiCMOS receiver prototype. The receiver employs a 2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> order sub-harmonic mixer that allows the use of a 100-GHz LO signal generated by HBT's to reduce DC power consumption. Additionally, the receiver employs a single mixer instead of I/Q down converter to further lower DC power consumption by reducing the number of LO chains and eliminating the need for the generation of I/Q LO signals. The receiver fabricated in a GF BiCMOS process with 45-nm CMOS and HBT fT/f<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> of 410/610 GHz exhibits a 16-GHz bandwidth, a single side band noise figure of 23 dB, OPldB of 0.5 dBm and an out-of-band gain roll-off of ~10 dB over 15 GHz at RF while consuming 96 mW not including that for an ADC.

We discuss the issues related to fabrication of InP based MMICs for government and commercial production applications. InP based MMICs offer unique advantages for many government systems which include lower noise figure, lower DC power consumption and higher linearity. Under the MAFET program, TRW is bringing both InP HEMT and InP HBT-based MMICs from a R&D state into production capability. Manufacturing issues will be addressed from a critical node point of view, where critical nodes are defined as those process steps with the greatest impact on the MMIC performance and yield.

An AlGaAs/InGaAs metal-oxide-semiconductor pseudomorphic high electron mobility transistor (MOS-PHEMT) single-pole-double-throw (SPDT) switch using Al 2 O 3 high-κ gate dielectric by atomic layer deposition is fabricated. The MOS-PHEMT exhibited a comparable dc performance and a much lower gate current compared to PHEMT. Radio-frequency (rf) test shows that the MOS-PHEMT switch has an insertion loss of less than 0.5 dB, an isolation larger than 30 dB, a return loss larger than 15 dB, and an input power for 1 dB compression of 31.4 dBm at 2.5 GHz. Overall, MOS-PHEMT monolithic microwave integrated circuits switches have comparable rf performance to PHEMT switches but with much lower dc power consumption.