Gate Diffusion Input Technique-Applications and Modifications: An Overview

In this paper, comparison of various full adder circuits is analysed. Pull Adder circuits are extensively used in digital design. Here different types of full adder such as Conventional CMOS, based on Ex-OR/Ex-NOR, Pass Transistor Logic(PTL) and Gate Diffusion Input (GDI)technique are done. Prom this, GDI technique takes less number of transistors and therefore consumes less power. In GDI-14T, 12T which is based on MUX and a proposed 10T is implemented. The power consumption is less for 12T whereas better output is obtained for 10T. Simulation results are obtained in 180nm technology using Mentor Graphics Tool.

Carry select adder (CSLA) one of the fastest adders used in complex data processing to perform fast arithmetic functions. Minimum amount of power consumption is a major driving force behind the development of CMOS technologies. From the structure of CSLA it is clear that there is scope for reducing the area & power consumption in the CSLA. In this paper 8T full adder is used as a building block for 8-bit SQRT CSLA. 8T full adder is designed by XNOR-XNOR hybrid CMOS design. Based on this modification, 8-, 16-, 32-, 64-bit SQRT CSLA architecture has been developed & compared with the regular SQRT CSLA. Binary to Excess one converter (BEC) based CSLA are analyzed to study the data dependence & to identify all redundant logic operations. In this paper, all the redundant logic operations in the conventional CSLA are eliminated and a new logic formulation where carry select operation is scheduled before the calculation of final sum is proposed. Gate Diffusion Input (GDI) technique of low power digital combinatorial circuit design is also described. The frequency of operation is 5 MHZ. This work estimates the performance of the proposed design with the regular design in terms of area & power through the logic design & layout in 250nm CMOS process technology & implemented using Tanner (S-Edit) tool. The result analysis shows that the proposed structure is better than the conventional CSLA.

This paper presents possible designs for high speed error tolerant adder using Gate Diffusion Input (GDI) technique. The 1-bit modified full adder (MFA) proposed in [1] is implemented using GDI technique (GDI-MFA). The GDI-MFA is extended to implement a 16-bit high speed error tolerant adder (GDI-HSETA). The performance of various configurations is studied based on metrics such as delay, area and power dissipation. The circuits have been simulated using pSPICE software. From the results it is observed that the proposed GDI-MFA has 52% less transistor count and consumes 33% less power compared to conventional adders. Results of simulation of GDI-HSETA and other adders in pSpice indicate that the proposed adder has 21.6% power reduction and 13% less transistor count. Also, based on the implementation of GDI-HSETA and existing 16-bit adders on FPGA Spartan 6 platform, it is observed that GDI-HSETA achieved power reduction compared to 16-bit adders using conventional design.

Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI(Gate Diffusion Input) Technique. Modified GDI is a novel technique for low power digital circuits design further to reduce the swing degradation problem. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder.This technique can be used to reduce the number of transistors compared to conventional CSLA and made comparison with known conventional adders which gives that the usage of carry-strength signals allows high-speed adders to be realised at lower cost as well as consuming lower power than previous designs. Hence, this paper we are concentrating on the area level &we are reducing the power using modified GDI logic.

GDI (Gate Diffusion Input) - a new technique of low power digital circuit design is described. This technique allows reducing power consumption, delay and area of digital circuits, while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various PTL design techniques is presented, with respect to the layout area, number of devices, delay and power dissipation, showing advantages and drawbacks of GDI as compared to other methods. A variety of logic gates have been implemented in 0.35 /spl mu/m technology to compare the GDI technique with CMOS and PTL. A prototype test chip of 8-bit CLA adder has been fabricated, based on GDI and CMOS cell libraries, showing up to 45% reduction in power-delay product in GDI. Properties of implemented circuits are discussed, simulation results are reported and measurements of a test chip are presented.

In this paper, we present the implementation of high speed 16-Bit CRC Generator architecture using gate diffusion input technique. The main objective of CRC generator is used for error detection in communication systems. The Gate Diffusion Input logic is a technique that are used to reduce transistor count and power consumption of sequential circuits. The hardware component of CRC is consists of group of D flip-flops. Here the gate diffusion input logic based D flip-flop is a basic cell to design a CRC Generator, maintaining low complexity of logic design. The design of 16 Bit CRC generator using GDI technique reports 59.95 % improvement in power consumption and 19% reduction in transistor count compared to conventional CMOS technique.

This paper proposes two novel approaches: a signed–unsigned modified Booth decoder/encoder that is used for the production of partial products and a 5-2 compressor for the addition stage of partial products. The improvement of a circuit can be done at the transistor level and the gate level. To improve the circuits at the gate level for the modified Booth decoder/encoder, a new table was designed and also the 5-2 compressor was obtained by changing the truth table. Speed, power consumption and area were improved in the proposed structures. In this paper, at the transistor level, the gate diffusion input (GDI) technique was used to implement logical gates and the gate-level delay of the GDI structures was also calculated. The results indicated that the proposed 5-2 compressor had a delay of 119 ps with a power consumption of 65[Formula: see text][Formula: see text]W, which shows a 23.5% improvement in power delay product (PDP) compared to the best structure in the comparison table, whereas the proposed Booth decoder/encoder had a delay of 257 ps with a power consumption of 61.74[Formula: see text][Formula: see text]W and shows a 63.7% improvement in PDP compared to previous studies. By using the proposed structures in the multiplier, a 22% improvement in PDP was observed. To simulate the obtained structures, the TSMC 0.18 and 0.09[Formula: see text][Formula: see text]m technologies and the HSPICE software were used. Cadence software was used to implement the layouts of the proposed structures.

Vedic maths is an ancient mathematical theory based on 16 sutras that has a unique computation technique. We employ the fourteenth sutra, 'Urdhva Tiryakbhyam', from the 16 sutras. Multiplication can be done 'vertically and crosswise' using this sutra. The creation of a high-speed Vedic Multiplier based on ancient Indian Vedic Mathematics principles that have been tweaked to boost efficiency. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. Multipliers are used in high-speed arithmetic logic units, multiplier and accumulate units, and other similar applications. With the rising limits on latency, the design of faster multiplications is becoming increasingly important. Many changes are being done to improve speed. Vedic multipliers based on Vedic Mathematics are among them. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. CMOS (Complementary metal-oxide-semiconductor) designs take up more space and use more energy. Power dissipation causes an IC to heat up, which has a direct impact on its reliability and performance. Gate Diffusion Input (GDI) technology reduces the size, propagation delay, and power consumption of digital circuits while also lowering logic complexity as compared to traditional CMOS and existing pass transistor logic approaches. We compared a 2x2 Vedic multiplier based on the GDI and mGDI (Modified GDI) techniques in this study. In comparison to the GDI approach, the mGDI technology employs much less transistors. The Vedic multiplier is implemented in the cadence virtuoso tool, on 180nm and 90nm technology.

Addition is an essential arithmetic operation that is used extensively in processing of digital information. Now a days approximate computing is emerging methodology in area of low power VLSI design that trades off accuracy for faster and power efficient designs. Accuracy Configurable Approximate Adders is an attractive option that provides a flexibility to user to configure adder as accurate or approximate. This paper presents a new Carry Maskable Adder realization based on Full Swing-Modified Gate Diffusion Input (GDI) technique. Proposed design is functionally verified through simulations in LTspice XVII. The performance comparison of proposed design with CMOS based counterpart show that the percentage reduction in delay is 32% while power consumption is reduced by 45%.

This paper evaluates the performance of the gate diffusion input technique (GDI) on self-checking and self-resetting logic (SRL) GDI technique of carry select adder (CSA) and carry look-ahead adder (CLA) for different word lengths. In the proposed design adapting level restoration technique eliminates conductance overlap between n-MOS and p-MOS devices. The various self-resetting logic implementations for self-correcting of carry select adder and carry look-ahead adder can detect all single stuck faults in normal operation mode. Besides, two rail encoding technique is used in carry select adder are used for multiple error detection/correction. The SRLGDI setup consists of a pair of full adders, multiplexers, two rail checking, and self-resetting logic. In this technique, the self-checking carry select adder is used for reducing area and self-resetting improves the performance of the adder. The analysis of CSA and CLA with 180nm technology is simulated by using Cadence tools. The delay reduction is 12.836% for 8-bit CLA using SRL GDI, power reduction is 27.55% for 8-bit CSA using SRL-GDI compared to the gate diffusion input technique. This GDI technique implementation saves the average energy consumption up to 31.14% in CSA and 32.83% in CLA making it suitable for power optimization in high speed VLSI systems.

The signal processing system is extremely popular in this day and age. All of the primary circuits in the digital signal processing system are built around the adder, which is the fundamental building block. Today’s needs for lowering the delay, space, and power consumption of adder circuits boost the overall efficiency of the system, propelling it to the next stage of technological development. Despite the fact that the Carry Select Adder (CSLA) takes up more space, it is being utilised in place of the ripple carry adder in order to reduce propagation delays. In other models, a Carry Select Adder based on a Binary to Excess-I Converter (BEC) was utilised, which required fewer logic resources than a standard CSLA and was hence more energy efficient. The fact that these CSLAs reject one sum after the calculation, however, means that they are not more efficient. As a result, the delay was not significantly decreased. It is necessary to apply the reduced logic CSLA in order to overcome this challenge. However, by employing the Gate Diffusion Input (GDI) Technique, it is possible to achieve a lower delay than the previously suggested reduced logic CSLA. The suggested technique consumes less power and has a shorter propagation latency than existing techniques. In addition, the number of transistors necessary for the circuit was reduced by implementing this GDI-based CSLA. It is possible to create an efficient adder using this technique, as seen above.

Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style

GDI (Gate Diffusion Input) is a new technique of low power digital circuit design is proposed. This technique allows minimization of area and power consumption of digital circuits. In this design XOR gate is designed using 3 transistors and CMOS full adder is designed based on two 3T XOR and one 2T Mux. Using 8 transistors the full adder is designed in this paper and voltage scaling also done by reducing supply voltage. In this proposed full adder, the power consumption 4.604μW is achieved and the total area is 144μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

The most significant challenge in designing adders using the gate diffusion input (GDI) technology is minimizing the anticipated area, power consumption, and propagation delay. In this article, we have compared both the Half Adder (HA) and Full Adder (FA) circuits using the GDI technique. After simulation, it was determined that the HA circuit performed better in terms of power, delay, power delay product (PDP), and energy-delay product (EDP), while the FA circuit consumed a larger area for its design. The PDP of the HA circuit at 1 V is $2.237\times 10^{-16}{\mathrm{J}}$, at 0.9 V it is $1. 549\times 10^{-16}J$, and at 0.8 V it is $1. 259\times 10^{-16} {\mathrm{J}}$, respectively. The EDP at 1 V is $50.057\times 10^{-22}$, at 0.9 V it is $23.995 \times 10^{-22}$, and at 0.8 V it is $15.850\times 10^{-22}$, respectively. These HA and FA circuits may find applications in both biological and medical healthcare applications.

Efficient GDI-based approximate subtractors for change detection in bio-image processing applications