Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design

This Special Section considers several studies that emphasize cross-domain physical optimization. The first paper applies physical optimization techniques that cut across the discrete and continuous domains; a geometric programming method is applied to solve the classical floorplanning problem. The second paper introduces a subfield scheduling approach that considers both ebeam lithography throughput and the thermal effect in the ebeam writing process. The third paper presents techniques that make the circuit layout compatible with multiple-patterning lithography. The fourth paper describes an integrated design methodology for microfluidic chips that encompasses operation scheduling, chip layout generation, control pin assignment, and wiring solution. The fifth paper crosses the boundaries of datapath design and random logic; it proposes a placement flow that simultaneously places a mixture of random logic and datapath cells found in hybrid designs. The short paper replaces flipflops with pulsed latches, and utilizes the time-borrowing property of pulsed latches and clock gating to achieve power efficiency.

An automatic alternative phase shift mask (PSM) pattern layout tool has been newly developed. This tool is dedicated for embedded DRAM in logic device to shrink gate line width with improving line width controllability in lithography process with a design rule below 0.18 micrometers by the KrF excimer laser exposure. The tool can crete Levenson type PSM used being coupled with a binary mask adopting a double exposure method for positive photo resist. By using graphs, this tool automatically creates alternative PSM patterns. Moreover, it does not give any phase conflicts. By adopting it to actual embedded DRAM in logic cells, we have provided 0.16 micrometers gate resist patterns at both random logic and DRAM areas. The patterns were fabricated using two masks with the double exposure method. Gate line width has been well controlled under a practical exposure-focus window.

A symbolic layout methodology for large-scale data paths is proposed. A gate-level symbolic expression, the logic transformation diagram, is adopted as a layout input. A mask layout is automatically generated from the symbolic expression. A hierarchical design method is used in combination with a bit-slice regular structure and a performance-determining irregular structure. A 1-b field of the bit-slice structure is designed symbolically and then compacted, and finally the entire data path is generated. Performance-determining irregular macrocells, such as adders with carry-look-ahead (CLA) circuits, are handcrafted independently and combined with the entire data path at the final step. To achieve high density and high performance, effort is focused on optimizing the layout of the 1-b field. Iteration of the editing and compaction loop can be executed in a short turnaround time (TAT). By the proposed methodology, a data path containing 21 K transistors in a 32-b microprocessor has been successfully produced. Design productivity has been increased tenfold, achieving a layout density equivalent to that of the handcrafted design. >

Existing formal verification methods do not handle systems that combine state machines and data paths very well. Model checking deals with finitestate machines efficiently, but model checking full designs is infeasible because of the large amount of state in the data path. Theorem-proving methods may be effective for verifying data path operations, but verifying the control requires finding and proving inductive invariants that characterize the reachable states of the system.We present a new approach to verification of systems that combine control FSMs and data path operations. Invariants are specified only for a small set of control states, called clean states, where the invariants are especially simple.We avoid the need to specify the invariants for the unclean states by symbolically simulating over all paths to find the possible next clean states.The set of all paths from one clean state to the next is represented by a regular expression, which is extracted from the control FSMs. The number of paths is infinite only if the regular expression contains stars. The method uses a heuristic to generalize the symbolic state to cover all of the paths of the starred expression. We have implemented a prototype tool for guiding an existing symbolic simulator and verification tool and used it successfully to prove properties of the Instruction Fetch Unit of TORCH, a superscalar microprocessor designed at Stanford. With much less effort, we were able to find all the bugs in the unit that were found earlier by manually strengthening the invariants.

Data path circuits are regular and best placed in bit-sliced pattern for improved Quality of Results such as timing, power, congestion and area. The cells in a column of bit slice structure are normally aligned on control pins or clock pins for straight routes, reducing power. The traditional way of placing data path circuits, using separate data path placer and then bringing them as macro in main design has its significant disadvantages. It is important for modern day placement tool to place random logic and data path circuits concurrently respecting the regularity that a data path circuit has by placing them in bit-sliced manner. It is not only important to place the data path elements in bit-sliced pattern but also that structure has to be maintained throughout the flow. The different set of optimization tricks can be applied to different bits of data path which can destroy the identical footprints of cells in column and that brings challenge of maintaining pin alignment. In addition to that, in lower nanometer nodes, fixed physical only cells pre-placed throughout the core area pose challenge of keeping bit-sliced structure intact. A flow for handling data path circuits in a place and route tool along with an algorithm for bit slice tiling is being proposed in this paper which addresses the challenges mentioned above.

High-speed high resolution analog-to-digital converter (ADC) is the key design blocks in mixed-signal chip design since the ADC is an interface between digital signal processing systems and the analog world. With the rapid advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power ADCs that can be realized in a mainstream deep sub-micrometer CMOS technology. On the other hand, since analog circuits tend to be sensitive to fluctuations in temperature and the fabrication process, circuit designers are forced to allow for a wide margin to ensure the desired operation of all the chips under various conditions. Therefore, if the margins can be minimized, both reduction of power dissipation and a higher yield in mass production can be achieved. To tap onto the waves of the rapid booming wireless communication markets, high resolution and high speed A/D converter is required at very low power consumption. Providing the wanted resolution at the required speed for the minimum power consumption and silicon cost is what's driving the use of specific A/D architectures [1]. Architectures that have been applied include flash, subranging, successive approximation, sigma-delta and pipelined. Each of these architectures has their specific advantages and drawbacks. Pipelined architecture poised as a suitable candidate since the power consumption will be an order of magnitude better comparing to flash ADC, subranging ADC, successive approximation ADC and oversampling ADC. Moreover, a correction algorithm can be employed to compensate for the errors in the sub-ADC. Shooting for even higher speed, parallelism is required to be incorporated into pipelined structure. Hence, in this work, a feasibility study of a novel subranging pipelined A/D converter with 100 MS/s and 8-bit resolution is conducted. This research describes the design of a 8-bit 100 MS/s subranging pipelined analog-to-digital converter(ADC) suitable for wide-range applications. To achieve the wide-range performance, this work purposes a novel architectural design at both system and circuit levels. At the device level, device modeling and active components characterisations are carefully studied. Thin gate oxide, NFET is fabricated in Chartered 90nm CMOS process. The results showed that the models used in SPIC simulation correlate well with the measured results except at the end of high VDD where breakdown is seen in the measured results but not during simulation. At the circuit level, a 3-bit coarse ADC and a 6-bit fine ADC are developed. Logic designs are also carried out. At the system level, this work investigates the effects of ADC design parameters such as DNL and INL in the static DC aspects and SFDR and ENOB in the dynamic AC aspects. A top-down design methodology is adopted in this work. The behavioral modelling results verify the success of the proposed architecture. The simulation results showed that the designed ADC is able to achieve a 7.4 effective bits out of 8 bit resolution.

A basic CAD-tool using a simple grid-like floorplan for placement of cells of varying sizes is presented. It is focused on the generation of physical and behavioural descriptions of data paths but is also suitable for random logic, data path controllers containing PLA's, registers, counters etc. and for analog designs containing OP's, capacitors etc. Two different types of floorplans can be chosen; one resembling the standard cell design approach and one resembling the bit-slice approach. By not assembling the cells with abutment, existing general purpose cell libraries can be used. An easy modifiable interpreting lisp-like language is used as input. Three design examples are discussed, one data path for a decimation filter, one data path for a Viterbi receiver and one multiplier.

In the EPS Core Ground Segment (CGS) network, IP multicast combined with the Pragmatic Generic Multicast (PGM) protocol is deployed to provide reliable point -to multipoint delivery of raw payload data streams from the ground stations to the central site, and of product data streams from the central site to users. The data streams are characterised. An overview is provided of the requirem ents and the design logic that have lead to the reliable multicast based solution being selected. Relevant technical detail is presented of the PGM/IP multicast configuration in the specific context of the EPS CGS network, characterised by multi -megabit da ta rates, local and wide -area network links - the latter of which a combination of terrestrial and satellite - and the presence of firewalls in the data path. With the data streams now being supported since the CGS validation and launch campaigns, and thro ughout the commissioning and routine operations phases, report is given on the experiences made so far. Performance and robustness is discussed as it has been achieved under nominal and deteriorated network conditions, versus the expectation to provide con tinuous reliable, lossless transmission. Issues that are specific to reliable multicast are highlighted, along with tuning and optimisation measures implemented to solve them. An outlook is provided on further enhancements planned. Based on the experiences gained, an assessment is made of the benefits and drawbacks of using reliable multicast in the CGS. As part of this assessment, the suitability of the solution to future EPS requirements is addressed.

In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both and global. In particular, flexible gate sizing, net buffering and detail placement require a certain amount of unused space in every region of the die. The need for local whitespace is further emphasized by temperature and power-density limits. Another requirement, the stability of placement results from run to run, is important to the convergence of physical synthesis loops. Indeed, logic resynthesis targetting congestion in a given placement or particular critical paths may be irrelevant for another placement produced by the same or a different layout tool. In this work we offer solutions to the above problems. We show how to tie the results of a placer to a previously existing placement, and yet leave room for optimization. In our experiments this technique produces placements with similar congestion maps. We also show how to trade-off wirelength for routability by manipulating whitespace. Empirically, our techniques improve circuit delay of sparse layouts in conjunction with physical synthesis. In the context of earlier proposed techniques for mixed-size placement, we tune a state-of-the-art recursive bisection placer to better handle regular netlists that offer a convenient way to represent memories, data paths and random-logic IP blocks. These modifications and better whitespace distribution improve results on recent mixed-size placement benchmarks.

OASIS is a cell-based silicon compiler system that supports rapid implementation of digital Application specific ICs (ASICs). The system automates the design process by taking a high-level language description and producing a layout of a testable IC. OASIS facilitates design of large digital systems on silicon and gives the designer sufficient control to enable exploration of the speed-versus-area design tradeoffs. The front end of OASIS is the LOGIC-III compiler that translates a high-level language description into a hierarchical netlist of gates. The LOGIC-III language is a PASCAL-like language that allows the designer to specify his design completely and in a uniform, consistent manner. The language supports both the logic synthesis for FSMs and combinational logic, and the structural/algorithmic synthesis of data paths and regular structures such as adders or multipliers. The OASIS system comprises an integrated set of tools for complete design, simulation, verification, layout and testing of ASICs. Experience with the system shows a marked increase in design productivity when compared with more traditional design techniques. The authors describe the system with its unique features and present some of the results of using OASIS in designing semi-custom ASICs. >

An accurate model is presented for the prediction of physical design characteristics, such as interconnection lengths and layout areas, for standard cell layouts. This model produces accurate shape constraint functions (height versus width of the layout over a range of aspect ratios) by considering the logic design specification, the physical design process, and the physical implementation technology. Random and optimized placements, global and detailed routing are each abstracted by procedural models that capture the important features of these processes. Equations that define the procedure model are presented. Predictions of layout characteristics that are within 10% of the actual layouts are achieved over a range of circuit functions and sizes. The authors have verified both the global characteristics (total interconnection length and layout area) and the detailed characteristics (wire length and feedthrough distributions) of the model. Accurate prediction of physical design characteristics is useful for floorplanning, evaluating the fit of a logic design to a fabrication technology, and studying placement algorithms. >

Logic design strategies

The random logic portion of a chip Implementing a set of Boolean functions and sequential circuits usually represents a major contribution to chip area. Obviously, there are many circuits which realize the same Boolean function. Unfortunately, at present there is no general theory that provides designers (and design automation programs) with lower bounds for total area, for gate oxide area, and for delay time of logic Implementations in Integrated systems. Therefore, the main task for the computer optimization program appears In choice of the circuit with the most convenient layout.DIADES is a design automation system with register-transfer level description on its Input and CIF file on output [5]. The digital circuit can be described in both behavioral and structural mode. A set of successive compilations and hardware implementing and optimizing transformations create the description of the network on the level of logic gates and pass transistors. As the output of hardware compilation from the higher level, this description is usually nonoptimal and thus is next optimized by recursive technology independent transformations based on Boolean algebra (like A*O = O, A*A = A, etc.). Inverters are also inserted into long chains of AND or OR gates, being the results of iterative circuits' compilation [4].The next stages are: technology dependant optimization of the logic network, and network's layout. It is assumed that the resultant network is multilevel, consists of complex negative gates, and is realized in semiregular Weinberger-style gate matrix layout. The logic minimization method intended for layout minimization is described in this paper.It is assumed in our silicon compiler, that logic is constructed of n-channel, polysilicon gate MOSFET ratioless complex gates, performing any negative function. By negative function we understand negation of positive function, while positive function is any combination of AND and OR functors [1]. Functions for evaluation of circuit's performance parameters such as total area, area of gate oxide, and gate delay time are used. These functions are defined in terms of basic technology and selected topology parameters. The method can be adapted to other technologies.

Design complexity is ever increasing with multi- mode, statistical timing analysis, multi-vt/VDD low power and multi-core performance based type of designs. IEEE 1800 system verilog (Ref 1) is a natural smooth transition language to verilog (Refi and 3) for system level design and verification. Verilog RTL has been popularly used for many design tape outs. System verilog (SV) extensive support exists in verification tools viz. simulators, formal for various powerful SV specific design constructs. It is envisaged that SV will be used for design tape outs soon as many design houses started using SV specific RTL constructs for system designs involving high levels of design data abstractions for various design application keeping in view of verification support. This paper analyzes on various SV design specific constructs for design quality of results (QOR) improvement. The specific constructs discussed for design QOR improvements are 1) operator overloading using user defined types to bring in efficient implementation of data path operators like multiplier, adder, shift,.. 2) Parameterized module interface for different sized datapath, memory, fifo, register files.. 3) Configuration to bind a particular efficient architecture to a module based on QOR requirement 4) System level modules interface and arbitration using "interface"construct. 5) Multiple clock domain definition and interface. 6) IEEE1801 UPF low power design intent flow.

The authors present an integrated tool set to generate highly optimized hardware computation blocks from a C language subset. By starting with a C language description of the algorithm, they address the problem of making FPGA processors accessible to programmers as opposed to hardware designers. Their work is specifically targeted to fine grained FPGAs such as the National Semiconductor CLAy/sup TM/ FPGA family. Such FPGAs exhibit extremely high performance on regular data path circuits, which are more prevalent in computationally oriented hardware applications. Dense packing of data path functional elements makes it possible to fit the computation on one or a small number of chips, and the use of local routing resources makes it possible to clock the chip at a high rate. By developing a lower level tool suite that exploits the regular, geometric nature of fine grained FPGAs, and mapping the compiler output to this tool suite, they greatly improve performance over traditional high level synthesis to fine grained FPGAs.