Gated body-biased full adder

Paper reports a novel majority function based current mode operated compact sized robust design of 1-bit full adder (FA) circuit. The focus of this work is to reduce the power supply consumption required for performing arithmetic operations by introducing a novel and efficient way of computing 1-bit addition relying on current mode operation. Presented high speed FA design utilizes only 7Ts, per bit, to implement sum and carry functions. The majority function based proposed FA circuit requires lesser number of transistors as compared to the conventional 28Ts FA circuit. A current mirror (CM) circuit has been incorporated in the proposed design to act as a constant current reference to drive the whole circuitry. Further, to evince the uniqueness of the proposed FA design, comparisons have been drawn with various other standard FA designs in terms of different design metrics such as power consumption, supply voltage requirement, power delay product (PDP), energy delay product (EDP) and operating speed. Extensive simulations have been performed using Virtuoso Analog Design Environment of Cadence @ 90 nm technology to verify the proposed design.

Background: Full adder is the key element of digital electronics. The CNTFET is the most promising device in modern electronics. To enhance the performance of the full adder, CNTFET is used in place of the CMOS. Objective: To implement the high speed full adder circuit for advance applications of the digital world. Methods: Full adder circuit with a new Gate diffusion technique has been implemented in this work. This is a comparative study of the 10-T CNTFET full adder with GDI technique and the 10-T Finfet based full adder using GDI technique. Ultra-low-power feature is the additional advantage of the GDI technique. This technology provides the full swing voltage to the circuit. Moreover, it also reduces the number of transistors required. This technique has been used with CNTFET to upgrade the full adder in terms of the dissipated power and product of power consumed and delay introduced in the circuit. Results: The proposed design shows that the low power dissipation comes out to be approximately 4.3nW at 0.5volts. The power delay product is 4.7x10-20 J at the same voltage level. The FinFET design also shows the better performance with GDI. But GDI enhances CNTFET based design power consumption by about 32% from the FinFET. Conclusions: CNTFET showed a better response due to good current conductivity as compared to the FinFET. This work has been implemented and simulated on the 32nm node technology.

Adders are plays a vital role in digital and vlsi systems. Arithmetic operations are an essential part of digital systems. During VLSI systems, the entire research is on lowering the scale of transistors for enforcing any other digital system. This proposed architecture implemented by different types of logic systems; each logic performs the different role in the hybrid system. The hybrid Full Adder cell with one bit is implemented in this structure. The proposed method is investigated using 22-nm CMOS hybrid full adder. The proposed architecture demonstrates substantial efficiency in power consumption and delay, based on simulation results. The simulation result expressed that the full adder circuit is used to modern high speed central processing unit in the data path architecture. This form of hybrid Full Adder, reduces the delay and increasing efficiency and mainly used in nano technology applications. The average power consumption of $1.1055 {\mu}\mathrm{W}$ with moderately low delay of 7.0415ps was found to be extremely low for 0.8-V supply at 22-nm technology. These kind of adder allocates significant improvements in power, high speed and area compared with previous full adder designs.

This paper, proposed a hybrid full adder with low power and less area using 8 transistors. Majority not gate and GDI techniques are collectively used for design this hybrid full adder. Some beforehand composed cells endure from non-full swing output, low speed, and high power utilization issues. While the new full adder has insignificant range overhead, it has enhanced the power Utilization of the circuit when contrasted with other full adder circuit. We have verified this full adder by utilizing cadence virtuoso gpdk 180nm technology at 1.2V supply voltage.

In this paper, comparison of various full adder circuits is analysed. Pull Adder circuits are extensively used in digital design. Here different types of full adder such as Conventional CMOS, based on Ex-OR/Ex-NOR, Pass Transistor Logic(PTL) and Gate Diffusion Input (GDI)technique are done. Prom this, GDI technique takes less number of transistors and therefore consumes less power. In GDI-14T, 12T which is based on MUX and a proposed 10T is implemented. The power consumption is less for 12T whereas better output is obtained for 10T. Simulation results are obtained in 180nm technology using Mentor Graphics Tool.

Modular arithmetic computations are used widely in various data security and reliability techniques. Information security systems certainly benefit from the design of energy-efficient modular exponentiation architectures. The use of low-power logic adders to realize modular exponentiation operations is very essential in prospective cryptography contexts. In this paper, various full adder circuit designs are presented which are used in developing an energy efficient modular exponentiation architecture. Here, the full adder is designed using Register Transfer Level (RTL), Standard Logic Cell (SLC), Reversible Logic Gate (RLG), and Artificial Neural Network (ANN) logic methods. All full adder designs are imposed on modular exponentiation circuit to analyze performance metrics in terms of dynamic power dissipation, Figure of Merit, and Energy Delay Product. The Modular Exponentiation architecture is designed based on the above full adders and is simulated and synthesized using Xilinx Vivado Zynq-7000 family configurable device. From the synthesis results, the dynamic power dissipation, Figure of Merit (FOM), and Energy Delay Product (EDP) of the ANN Modular Exponentiation circuit shows an improvement compared to other designs. The total power consumption, dynamic power dissipation, FOM, and EDP of ANN Full Adder and Modular Exponentiation circuit can achieve (8%, 16%), (23.5%, 20.7%), (14.7%, 14%), and (28.5%, 16%) compared to RLG Full adder and Modular Exponentiation circuit.KeywordsFeynman gateMLPerceptronSwitching activityPDPModular multiplierToffoli gate

This research work focuses on implementation of the FinFET-based complementary metal-oxide-semiconductor (CMOS) Full Adder circuits for different transistor configurations using ASAP7 FinFET model. First, this work examines FinFET-based AND-OR-invert (AOI) gates using different topologies, and second, a FinFET-based CMOS Full Adder circuit at the 7[Formula: see text]nm technology node is analyzed with respect to its process, voltage and temperature (PVT) variability effect measured in terms of the normalized standard deviation of different performance metrics. The comparison is made between conventional (CFFA1) and proposed (FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8) FinFET-based CMOS full adder circuits. The aim is to determine the optimal design configuration of the FinFET full adder circuit with the minimum impact of PVT variability. On examining the power delay product (PDP) variability, it is found that variations in FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8 are significantly lower than CFFA1 by 6.30%, 4.68%, 10.30%, 65.48%, 68.05%, 65.61% and 17.20%, respectively. Among all the proposed configurations, normalized standard deviation [Formula: see text] for the PDP metric is lowest in FFA6, followed by FFA7, FFA5, FFA8, FFA4, FFA2 and FFA3. The normalized standard deviation [Formula: see text] for power dissipation, however, is lowest in FFA8. In addition, a layout comparison analysis of conventional and proposed full adder circuits reveals that FFA7 has the least area, followed by FFA8, FFA6, FFA5, FFA3, FFA4, FFA2 and CFFA1. The area of FFA2, FFA3, FFA4, FFA5 and FFA6 has decreased by 3.29%, 3.51%, 3.50%, 5.14% and 5.52%, while FFA7 and FFA8 have experienced a decrease in area by 13.87% and 14.36%, respectively, as compared to conventional CFFA1. The proposed layout of FinFET-based CMOS Full Adders can be directly transferred into the foundry’s production line for manufacturing purposes. The overall investigation led us to conclude that FFA8 is the most efficient of all due to the lowest power variation, lower delay variation and lower PDP variation, moreover it has a reduced layout area among all the discussed designs. However, there is a tradeoff in terms of penalty in nominal power, propagation delay and PDP in the proposed topologies.

Being one of the promising techniques for future computing systems, quantum-dot cellular automata (QCA)-based circuit design has gained massive interest among researchers due to which numerous QCA-based full adder (FA) circuits have been designed. Due to numerous QCA FA circuits available in the existing literature, researchers find it difficult to invest the time to search, implement, simulate, and analyze QCA FAs to find the best-suited design according to their needs. Existing review articles do not present a complete overview and performance comparison of QCA FAs. Also, the existing articles do not include quite a number of QCA FA designs in the literature review. As a result, a detailed review including all possible QCA FAs becomes essential. Therefore, rather than going for a new QCA FA design, this research aims to aid researchers by providing an extensive literature review and comprehensive study on existing QCA FAs. A total of 47 QCA FAs have been considered for analysis. The QCA FA implementation method and performance parameters are summarized in a tabular manner to provide a quick overview and comparison of the QCA FAs.

In this paper we present a novel high speed and ultra low-voltage full adder circuit based on ultra low-voltage semi floating-gate CMOS logic. The full adder circuit contains a high speed ultraslow-voltage carry generator circuit and a multiple-valued intermediate representation of the summation. The full adder is suitable for low-voltage serial full adder design. Simulated data presented is valid for a 90nm TSMC CMOS process.

In this paper we present circuit techniques for CMOS low-power high-performance multiplier design. Novel full adder circuits were simulated and fabricated using 0.8-/spl mu/m CMOS (in BiCMOS) technology. The complementary pass-transistor logic-transmission gate (CPL-TG) full adder implementation provided an energy savings of 50% compared to the conventional CMOS full adder. CPL implementation of the Booth encoder provided 30% power savings at 15% speed improvement compared to the static CMOS implementation. Although the circuits were optimized for (16/spl times/16)-b multiplier using the Booth algorithm, a (6/spl times/6)-b implementation was used as a test vehicle in order to reduce simulation time. For the (6/spl times/6)-b case, implementation based on CPL-TG resulted in 18% power savings and 30% speed improvement over conventional CMOS.

The VLSI based circuits often pose challenges in the form of various faults (such as transient faults, permanent faults, stuck-at-faults). These faults appear even after testing also. They occur because of reduction in the size of the circuit or during realtime implementation, as these faults are difficult to detect. It is very important to detect and rectify all such faults to make the system foolproof and achieve expected functionality. In this paper, 12 transistors based, full adder circuit (12T-FAC) using Carbon Nanotube Field Effect Transistor (CNFET) technology is proposed. The proposed design based on CNFET provides high fault resistance towards transient, permanent faults and works with least power, delay and power-delay product (PDP). Later, features like fault detection and correction circuit have been added in 12T-FAC. The final version of full adder circuit capable of correcting errors has been used in designing applications like multipliers. The proposed full adder circuit was designed with CNFET technology, simulated at 32 nm with supply voltage +0.9 V using the Cadence Virtuoso CAD tool. The model used is Stanford PTM.

In modern days, power dissipation is one of the biggest challenges in VLSI design. The numbers of transistors are reduced in the circuit and ultra-low power design. This chapter is based on full adders that are designed using EX-OR gates, and GDI technique is used for low power and delay in full adders. The main aim of this chapter was to reduce the power dissipation and area by reducing the number of transistors. Multipliers are the main sources of power dissipation in DSP. Braun Array is used to implement a multiplier, a relatively simple form of parallel adder. In our chapter, we designed a 4-bit Braun multiplier based on GDI and the simulations are performed by CADENCE VIRTUOSO based on 45-nm CMOS technology with the supply voltage of 0.7 V. The simulation results showed that proposed multiplier at 45 nm can reduced the average power from 291.4 to 133.9 nW, total power from 286.3 nW to 130.3 nW, static power from 1.15 nW to 4.10 pW, static current from 1.64 nW to 5.86 pW, and power consumption from 2.21 W to 1.009 W.

A conventional dual port 8-transistors (8T) SRAM circuit allows an asynchronous reading and writing feature, but its leakage power is significantly higher compared to the conventional 6T cell in the same technology. We proposed transistors stacking technique to reduce leakage power consumption in the fine-grained 8T cell’s read bitline. Furthermore, power gating and floating write driver techniques are proposed to further reduce the leakage power consumption in the bank-level wordline (WL) driver. Post-layout simulations show that the leakage power consumption of the 32-Kb SRAM is reduced by 75% in stand-by mode with only 13% read access time increase with 1.5% area penalty.

A problem inherent in power-gated circuits is the overhead of state-retention storage required to preserve the circuit state in standby mode. <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HLS</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pg</i> is a new design framework that takes power gating into account, from scheduling, allocation, and controller synthesis to the final circuit layout. Its main feature is a new scheduler that minimizes the number of retention registers required at the power-gating control step. In experiments on benchmark designs implemented in 0.9-V 65-nm technology, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HLS</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pg</i> reduced leakage current by 20.7% on average, with 5.0% less area and 4.1% less wirelength, compared to the power-gated circuits produced by conventional high-level synthesis.

In this chapter, we discuss two different designs of QCA Ripple Carry Adders by customizing the fundamental block, i.e., the full adder circuit. We start the discussion with designing RCA using 5-input majority gate-based full adder. Further, designs are evolved considering a compact form full adder that relied on a novel XOR structure. Parts of the analysis presented in this chapter have been discussed in [1, 2].