Gateless synchronous counters with D flip-flops

Many applications produce acceptable results when their underlying computations are executed in an approximate manner. For such applications, approximate circuits enable hardware implementations that exhibit improved efficiency for a given quality. Previous efforts have largely focused on the design of approximate combinational logic blocks such as adders and multipliers. In practice, however, designers are concerned with the quality of outputs generated by a sequential circuit after several cycles of computation, rather than an embedded combinational block. We propose ASLAN (Automatic methodology for Sequential Logic ApproximatioN), the first effort towards the synthesis of approximate sequential circuits. Given a sequential circuit and an output quality constraint, ASLAN creates an approximate version of the circuit that consumes lower energy, while meeting the specified quality bound. The key challenges in approximating sequential circuits are (i) to model how errors due to approximations are generated, re-circulate through the combinational logic over multiple cycles of operation, and eventually impact quality of the final output, and (ii) to select the most beneficial approximations, i.e., those that result in higher energy savings for smaller impact on quality. ASLAN addresses the first challenge by constructing a virtual Sequential Quality Constraint Circuit (SQCC) and utilizing formal verification techniques to ensure that the selected approximations meet the quality constraint. To address the second challenge, ASLAN identifies combinational blocks in the sequential circuit that are amenable to approximation, generates local quality-energy trade-off curves for them, and uses a gradient-descent approach to iteratively approximate the entire sequential circuit. We used ASLAN to automatically synthesize approximate versions of ten sequential benchmarks, resulting in energy reductions of 1.20X-2.44X for tight quality constraints, and 1.32X-4.42X for moderate quality constraints. We present case studies of using the approximate circuits generated by ASLAN in two popular applications - MPEG Encoding and K-Means Clustering - obtaining 1.32X energy savings with 0.5% PSNR degradation, and 1.26X energy savings with 0.8% increase in mean cluster radius, respectively.

The paper deals with synthesis of sequential circuits defined by their algorithmic state machine notation. Such circuits have a number of specific properties which enable efficient design of the circuits by utilizing so-called linearization techniques. A typical linearization technique includes calculation of autocorrelation values for a system of logic functions corresponding to the circuit. For the mentioned sequential circuits, the calculations which usually require massive computational recourses may be significantly reduced and thus low-overhead implementations of the circuits can be obtained relatively easy. The paper introduces a novel architecture of so-called linearized sequential circuits, and a piece-wise linearization approach for synthesis of sequential circuits. Results are evaluated both analytically and by using a number of standard benchmarks.

A description is given of SIS, an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table or a logic-level description of a sequential circuit, SIS produces an optimized net-list in the target technology while preserving the sequential input-output behavior. Many different programs and algorithms have been integrated into SIS, allowing the user to choose among a variety of techniques at each stage of the process. It is built on top of MISII and includes all (combinational) optimization techniques therein as well as many enhancements. SIS serves as both a framework within which various algorithms can be tested and compared and as a tool for automatic synthesis and optimization of sequential circuits. >

State assignment is the most critical step in the synthesis and optimization of sequential circuits as it significantly impacts sequential circuits area and power. Due to the high complexity of the state assignment problem and the ineffectiveness of existing deterministic algorithms in generating good solutions, evolutionary algorithms can be employed to obtain more effective state assignment solutions. In this paper, we propose a probabilistic tabu search (PTS) state assignment algorithm that is employed for the optimization of area and power of sequential circuits. The proposed algorithm is based on tabu search with the addition of exploiting code swap probabilities to prune the search space more effectively. Code swap probabilities are updated dynamically during the execution of the algorithm in such a way that code swaps that result in relatively inferior solutions will be assigned lower probabilities while those that result in good solutions will be assigned higher probabilities. In addition, tabu list size is changed dynamically during execution to help the algorithm get out of local minima. Based on experimental results, we show that the proposed PTS state assignment algorithm is more effective than all existing state assignment algorithms as it generates state assignment solutions with significantly lower area and power.

A method of synthesis and decomposition of autonomous linear sequential circuits

This paper considers the general problem of the synthesis of asynchronous combinational and sequential circuits based on the assumption that gate delays may be unbounded and that line delays are suitably constrained. Certain problems inherent to circuit realizations with unbounded gate delays are discussed and methods of solving them are proposed. Specific synthesis techniques are presented for both combinational and sequential circuits. The use of completion detection necessitated by the assumption of unbounded gate delays also causes the circuits to stop operating for approximately half of all possible single faults, thus achieving a degree of self-checking.

An approach to logic synthesis of digital synchronous sequential circuits is presented. Algorithms are described for minimizing the area of synchronous combinational and/or sequential circuits under cycle time constraints and for minimizing the cycle time under area constraints. It is shown how to optimize concurrently the circuit equations and the register position by a set of algorithms based on logic transformations. An implementation of the algorithms in the program Minerva is described, and experimental results are reported.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A new approach is presented to logic synthesis of digital synchronous sequential circuits. The authors describe algorithms for minimizing (i) the area of synchronous combinational and/or sequential circuits under cycle time constraints, and (ii) the cycle time under area constraints. Previous approaches attacked this problem by separating the combinational logic from the registers and by applying circuit transformations to the combinational component only. The authors show instead how to optimize concurrently the circuit equations and the register position. This method is novel and can achieve results that are at least as good as those obtained by previous methods. A computer implementation of the algorithms in the Minerva program is described. >

In this paper, we present a procedure for realizing any normal mode flow table by an asynchronous sequential circuit with a single pure delay, so that no hazards are present even if several input variables change in a transition. A modification of Unger's single delay realization is also proposed in order to allow several inputs to change in a transition without producing output transients. We also show how any normal mode flow table can be realized without inserted delay elements if a restriction on the relative magnitudes of line and gate delays is satisfied and only one input variable is allowed to change in a transition.

Using binary decision diagrams for representation and analysis of communication protocols

The theoretical basis of sequential circuit synthesis is developed, with particular reference to the work of D. A. Huffman and E. F. Moore. A new method of synthesis is developed which emphasizes formal procedures rather than the more familiar intuitive ones. Familiarity is assumed with the use of switching algebra in the synthesis of combinational circuits.

This paper presents a procedure for synthesizing multilevel circuits with concurrent error detection based on Bose-Lin codes (1985). Bose-Lin codes are an efficient solution for providing concurrent error detection as they are separable codes and have a fixed number of check bits, independent of the number of information bits. Furthermore, Bose-Lin code checkers have a simple structure as they are based on modulo operations. Procedures are described for synthesizing circuits in a way that their structure ensures that all single-point faults can only cause errors that are detected by a Bose-Lin code. This paper also presents an efficient scheme for concurrent error detection in sequential circuits. Both the state bits and the output bits are encoded with a Bose-Lin code and their checking is combined such that one checker suffices. Results indicate low area overhead. The cost of concurrent error detection is reduced significantly compared to other methods.

A method for synthesizing sequential circuits with testability in the level of state transition table is proposed. The state transition table is augmented by adding extra two inputs so that it possesses a distinguishing sequence, a synchronizing sequence, and transfer sequences of short length. By using suitable state assignment codes sequential circuits with shorter test sequences and with fewer gates are realized. Some experimental results for small benchmark circuits are shown. >

Safety-critical systems used in applications that demand high levels of dependability, efficiency, and fault-tolerance often use sequential logic circuits in its design and implementation. The safety-critical digital system typically uses latches, flip-flops, and other memory elements, which are prone to the effects of natural faults and single event upsets (SEUs) caused by radiation-induced effects. The faults can lead to subsystem failures due to the continuous advancement in the realization of the small size transistor. To design a reliable digital-based system, it is essential to develop new fault-tolerance approaches that are integrated into the design of sequential logic circuits. This work proposes a novel fault-tolerant approach based on the redundancy of sequential logic circuit, which consists of a variety of design components, D flip-flop storage elements linked to a fault injection unit, a duplicate modular redundancy, and data monitoring units with a switching circuit. The experimental simulation results using a five-state Markov chain analysis model prove that the proposed fault-tolerant system can achieve 0.99999998 for reliability of the fault detection coverage (C) which equal to 0.99999. Finally, we believe that using this new approach of fault-tolerance and redundancy would improve the dependability and reliability of next generation safety-critical applications.

Our previous work focused on the synthesis of sequential circuits based on a partial input/output sequence. As the behavioural description of the target circuit is not known the correctness of the result can not be verified. This paper proposes a method which increases the correctness percentage of the finite-state machine (FSM) synthesis using multiple partial input/output sequences. The synthesizer is based on genetic algorithm. The experimental results show that the correctness percentage can be increased to 100% by increasing the number of input/output sequences.