Generic Mixed-Radix FFT Pruning

Recent research presents a technique to enumerate all valid assignments of “twiddle factors” for power-of-two fast Fourier transform (FFT) flow graphs. Brute-force search employing state-of-the-art Boolean satisfiability (SAT) solvers can then be used to find FFT algorithms within this large solution space which have desirable characteristics. Surprisingly, this approach has discovered FFT algorithms requiring fewer operations than the split-radix algorithm even when all twiddle factors are nth roots of unity. This paper reviews and then extends this prior research to examine fast discrete convolution algorithms when implemented via FFT and inverse FFT (IFFT) algorithms. In particular, we find that the combination of FFT and IFFT algorithms in fast convolution permits greater freedom when selecting valid twiddle factor assignments. We exploit this freedom and use SAT solvers to find new fast convolution algorithms with the lowest operation counts known.

This work presents simulation, analysis and experimental verification of Fast Fourier Transform (FFT) algorithm for shunt active power filter based on three-level inverter. Different types of filters can be used for elimination of harmonics in the power system. In this work, FFT algorithm for reference current generation is discussed. FFT control algorithm is verified using PSIM simulation results with DLL block and C-code. Simulation results are compared with experimental results for FFT algorithm using DSP TMS320F28335 for shunt active power filter application.

Signal source separation is an important aspect of both measurement and signature intelligence (MASINT) as well as modern commercial smart grid applications. In some MASINT scenarios, real-time signal processing is required in a small physical form factor, which can become prohibitive with the high sample rates required of modern signal identification algorithms. We develop a new Fast Fourier Transform (FFT) algorithm, the Aliased FFT (AFFT), that exploits spectral redundancy and sparsity in the signal to drastically reduce the number of computations required from O(N logN), for the normal FFT, to one that approaches the idealized O(K logK) for a K-sparse signal. We also develop a signal source separation algorithm using harmonically aligned signal projections (HASP) that is useful for transforming a one-dimensional signal of interest (SOI) into a two-dimensional image in such a way to facilitate automated feature extraction. An automated feature extractor is described which can accurately achieve super-resolution far beyond that of the traditional FFT by again taking advantage of the harmonic structure present in the SOI. We demonstrate HASP and this feature extractor for the application of load disaggregation-identifying the presence of certain types of devices connected to a power system.

The conventional method of frequency measurement based on traditional fast Fourier transform (FFT) can't provide to an ideal performance due to the fence effect and the leakage of frequency spectrum. As an improved algorithm of the traditional FFT, the all phase FFT (apFFT) spectrum analysis has a perfect performance on suppressing the spectrum leakage and the property of phase invariant. In this paper, a novel method for frequency measurement which takes the advantage of all phase FFT is proposed. This method utilizing two largest spectrum lines of the signal from time-domain provides a higher precision than traditional method. In the paper, a corresponding frequency measurement design based on Field Programmable Gate Array (FPGA) is implemented. The functional simulation results show that the design based on FPGA has better performance compared with the traditional method for frequency measurement.

Background: Fast Fourier Transform (FFT) processor is the important method in Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Split-Radix Fast Fourier Transform (SRFFT) estimates the least number of multiplications compared to other FFT algorithm; hence SRFFT is the best for the implementation of low power FFT processor. Methods: In this paper, the proposed “pipelined 32-point Split-Radix Multi-path Delay Commutator (SFMDC) FFT” architecture is designed. The MDC architecture has advantages in reducing the low chip area and lower power consumption. The SR-FFT algorithm has changing the numbers of butterfly elements in successive stages. The 32-point SR-MDC FFT architecture is to determine the frequency transformation techniques. The Split-Radix FFT algorithm is based on radix-2 and radix-4 algorithm and it is related to mixed radix FFT. Findings: The performance evaluation of proposed architecture is determined through VLSI System. Less area, low power consumption and high speed are the main parameters in this design. The proposed structure provides high throughput rate and low hardware complexity. Improvements: The goal of this proposed work is to reduce the slices and LUTs and power consumption and also to enhance the performances of the FFT processor than the existing method. The proposed method has been evaluated by using ModelSim 6.3C and synthesis results has been validated by using Xilinx Plan ahead 12.4.

The next generation Graphics Processing Units (GPUs) are being considered for non-graphics applications. Millimeter wave (60 Ghz) wireless networks that are capable of multi-gigabit per second (Gbps) transfer rates require a significant baseband throughput. In this work, we consider the baseband of WirelessHD, a 60 GHz communications system, which can provide a data rate of up to 3.8 Gbps over a short range wireless link. Thus, we explore the feasibility of achieving gigabit baseband throughput using the GPUs. One of the most computationally intensive functions commonly used in baseband communications, the Fast Fourier Transform (FFT) algorithm, is implemented on an NVIDIA GPU using their general-purpose computing platform called the Compute Unified Device Architecture (CUDA). The paper, first, investigates the implementation of an FFT algorithm using the GPU hardware and exploiting the computational capability available. It then outlines the limitations discovered and the methods used to overcome these challenges. Finally a new algorithm to compute FFT is proposed, which reduces interprocessor communication. It is further optimized by improving memory access, enabling the processing rate to exceed 4 Gbps, achieving a processing time of a 512-point FFT in less than 200 ns using a two-GPU solution.

In this paper we discuss the VLSI implementation of the new radix-2 Decimation In Time (DIT) Fast Fourier Transform (FFT) algorithm with reduced arithmetic complexity which is based on scaling the twiddle factor. Some signal processing require high performance FFT processors and to meet these performance requirements, the processor needs to be pipelined and parallelized. An optimized ASIC design is derived from this new radix-2 algorithm with fewer multipliers and adopted a complete parallel and pipelined architecture for hardware implementation of a 64 point FFT. The implementation results show that the proposed architecture significantly reduces the hardware area by 13.74 percent and power consumption by 16 percent when compared to the standard FFT architecture. Simulation of design units is done in Xilinx ISE WebPack 13.1 and synthesized using Cadence Encounter RTL Compiler.

This paper empirically evaluates a recently proposed Deterministic Sparse Fourier Transform algorithm (hereafter called DSFT) for the first time. Our experiments indicate that DSFT is capable of guaranteed general frequency-sparse signal recovery using subNyquist sampling for realistic bandwidth values. Furthermore, we show that both variants of DSFT have fast reconstruction runtimes. In fact, the sublinear-time DSFT variant is shown to be faster than a traditional Fast Fourier Transform (FFT) for highly-sparse wideband signals.

In recent past, we developed 4×8 and 4×16 processing element (PE) template-based Coarse-Grain Reconfigurable Arrays (CGRAs) and mapped different length and type of Fast Fourier Transform (FFT) algorithms on them. In this paper, we have considered radix-4 and radix-(2, 4) FFT accelerators which were generated from 4 × 8 and 4 × 16 PE CGRA templates respectively. We estimated their power and energy consumption while radix-4 accelerator was processing 64 and 1024 points and radix-(2, 4) accelerator was processing 64 and 128 points of FFT algorithms. The power consumption was estimated by timing simulation of postfit gate-level netlist of both of the accelerators for a Field Programmable Gate Array (FPGA) used as target platform. Based on the measurements, we have compared both of the accelerators for their power and energy consumption.

In Digital Signal Processing (DSP), Fast Fourier Transform (FFT) algorithm and its hardware implementation play a significant role. To implement FFT in hardware, fixed point arithmetic is preferred as it is simple to execute and also saves area and power. The finite bit representation of signals and coefficients in fixed point result in quantization error which degrades FFT performance mainly Signal to Quantization Noise Ratio (SQNR). In this paper, SQNR improvement in fixed-point FFT is achieved by modifying Radix-2 Decimation In Time (DIT) conventional butterfly structure.

This paper presents a scaled radix-2/8 fast Fourier transform (FFT) (SR28FFT) algorithm for computing length- N = 2m discrete Fourier transforms (DFTs) scaled by complex number rotating factors. The idea of the SR28FFT algorithm is from the modified split radix FFT (MSRFFT) algorithm, and its purpose is to furnish other algorithms with high efficiency but without shortcomings of the MSRFFT algorithm. A novel radix-2/4 FFT (NR24FFT) algorithm and a novel radix-2/8 FFT (NR28FFT) algorithm are proposed. These two algorithms use SR28FFT to calculate their sub-DFTs of odd-indexed terms. Several aspects of the two algorithms such as computational complexity, computation accuracy, and coefficient evaluations or accesses to the lookup table all are improved. The bit-reverse method can be used for their order permutation and no extra memory is required to store their extra coefficients by the two novel algorithms, which contribute significantly to the performance of the FFT algorithms. The SR28FFT algorithm can also be applied to other algorithms whose decomposition contains sub-DFTs of powers-of-two. The Appendix presents an algorithm named SR28FFT-2 for further reducing the number of arithmetic operations, and NR24FFT and NR28FFT algorithms based on SR28FFT-2 requires fewer real operations than that required by the MSRFFT algorithm.

Chapter 6 - Fast Fourier transform methods

Hw/Sw Co-Design technique for 2D fast fourier transform algorithm on Zynq SoC

In this paper, we propose higher point FFT (fast Fourier transform) algorithms for a single delay feedback pipelined FFT architecture considering the 4096-point FFT. These algorithms are different from each other in terms of twiddle factor multiplication. Twiddle factor multiplication complexity comparison is presented when implemented on Field-Programmable Gate Arrays (FPGAs) for all proposed algorithms. We also discuss the design criteria of the twiddle factor multiplication. Finally it is shown that there is a trade-off between twiddle factor memory complexity and switching activity in the introduced algorithms.

Fast Fourier Transform (FFT) is one of the core algorithms in digital signal processing. The traditional FFT processing method can no longer meet the data processing requirements, so the implementation and optimization of the better performance radix-4 FFT algorithm has very important research value. Based on FPGA technology, this paper proposes a design scheme of radix-4 FFT algorithm processing system. By optimizing the butterfly processing unit, the system realizes a high-performance FFT algorithm processing system with characteristics of faster operation speed, higher calculation accuracy, easy hardware implementation and large capacity compared with the traditional FFT processing method. It is well suited for scientific computing, image processing and other fields.