Glass Based 3D-IPD Integrated RF ASIC in WLCSP

As electronic products become smaller and thinner with increasing number of functions, the demand for high density and high integration becomes stronger. Glass has many properties that make it an ideal substrate for high integration substrate such as; ultra high resistivity, adjustable thermal expansion (CTE) high modulus, low dielectric constant, low dielectric loss and manufacturability with large panel sizes. Multi-bands with carrier aggregation, Wi-Fi/GPS coexistence, and LTE-U make RF front end more and more complicated. 3D IPD (integrated passive devices) on Glass substrate technology could be advantage solution include reducing power consumption and small form factor. This paper presents a demonstration of 3D RF front end filters using 3D solenoid inductors with through glass vias (TGV) and Cu-SiN-Cu MIM structure on Gen1 glass substrate (300mm × 400mm) panel format using color filter manufacturing line for flat panel display. For inductors, drastic performance (size and low resistance therefore high-quality factor) improvement have been demonstrated by technology evolutions from 3D solenoid using TGV with conformal Cu plating method, achieving low resistance of 3.1mohm per 70um diameter TGV on a 400um thick glass panel. This low-resistance TGV with 2.7mOhm/sq TGV connections on both sides of the glass substrate, record high inductor quality factor of 39 was obtained at 2.5GHz using five and half turn inductor of 7.9nH inductance, For capacitors, we have successfully integrated a Cu MIM (metal-insulator-metal) structure by using 15um thick Cu plates and dielectric, resulting in high capacitance density of 0.26nF/mm2 for RF application. By integrating TGV inductor-first and MIM capacitor-next, high-performance and high-density LC components are synthesized to perform as RF front end filters such as low-pass filters, diplexers, triplexers, and multiplexers. The 3D inductors, Cu MIM, LC resonators and filters were successfully integrated using glass panel manufacturing infrastructure for the first time. Process characterization and process control monitors were evaluated at the panel level to address high-volume and high-yield manufacturability of RF filters with the unprecedented filter performance in terms of insertion loss and out of band rejections in smaller form factor than any other technologies have achieved so far. Furthermore, the TGV filters were mounted on electrical evaluation boards as well as JEDEC standard testing boards to check any device-level, chip-level, and board-level reliabilities associated with glass or TGV materials as well as their interaction with Cu, SiN, polymer inter layer dielectric materials, and solder joints, showing no performance degradations during thermal cycling, drop shock, bending, or high-power testing situations.

Chip Scale Packaging (CSP) has captured the attention of every semiconductor and printed circuit board manufacturer, but relatively few CSPs are in full production. Unlike the PCB surface mount assembly process, the wafer level portion of the CSP industry (and in particular, the back end process) lacks standards. As a result, suppliers and customers have disparate requirements. This poses a unique challenge for CSP manufacturers and equipment suppliers to develop an integrated back-end-of-the-line that provides high volume and flexibility with little changeover time and low reconfiguration costs. The back-end process we describe includes polymer coating, solder ball placement, laser marking, singulation, testing, and tape & reel. All of these are performed at the wafer level. The polymer coating process is used to define the grid array openings on the packaged devices with 0.3 mm solder balls on 0.5 mm pitch. Laser marking is incorporated with the requirement of producing alphanumeric and two-dimensional cell codes on both silicon and glass wafers. The unique requirement for singulation is to minimize the displacement of bumped die during the dicing and cleaning process. This is to minimize potential misalignment of the die during test. In order to test a diced wafer at the wafer level, we have worked with a vendor to supply a handler that can accept dicing film frames and compensate for die misalignments. Lastly, traditional tape & reel machines are not suitable for bulk packaging of small, wafer level devices. We have purchased a modified die taping/sorting machine and have designed a custom tape pocket. All versions of the Intarsia wafer level CSP are fully surface-mount compatible and are designed to allow a wide assembly process window with existing placement equipment and technologies. Board level assembly issues unique to CSPs will be also discussed.

We present a novel method for the fabrication of void-free copper-filled through-glass-vias (TGVs), and their application to the wafer-level radio frequency microelectromechanical systems (RF MEMS) packaging scheme. By using the glass reflow process with a patterned silicon mold, a vertical TGV with smooth sidewall and fine pitch could be achieved. Bottom-up void-free filling of the TGV is successfully demonstrated through the seedless copper electroplating process. In addition, the proposed process allows wafer-level packaging with glass cap encapsulation using the anodic bonding process, since the reflowed glass interposer is only formed in the device area surrounded with silicon substrate. A simple coplanar waveguide (CPW) line was employed as the packaged device to evaluate the electrical characteristics and thermo-mechanical reliability of the proposed packaging structure. The fabricated packaging structure showed a low insertion loss of 0.116 dB and a high return loss of 35.537 dB at 20 GHz, which were measured through the whole electrical path, including the CPW line, TGVs and contact pads. An insertion loss lower than 0.1 dB and a return loss higher than 30 dB could be achieved at frequencies of up to 15 GHz, and the resistance of the single copper via was measured to be 36 mΩ. Furthermore, the thermo-mechanical reliability of the proposed packaging structure was also verified through thermal shock and pressure cooker test.

Most important technology for developing of wafer level packaging is studied in this paper. That is the process of drilling the via hole that are needed filling of conductive material for electrical connection or non-conductive material for reliability. Several kinds of drilling and filling methods of via holes for the interconnection were studied. The via formation for interconnection is based on smaller and lower cost package process. However, glass wafer which is substrate material of wafer level package for crystal unit device is difficult to make via by using novel method. The structure of wafer level crystal unit package for low cost and high performance is designed and optimized. The glass and Si wafer for package substrate and lid is chosen and considered as the structure for its mechanical and thermal strength and effective process of mass production. The interconnection via is formed through glass wafer by using sand blasting or laser drilling and Cu electro-plating method that enable the connection of the signal electrode on the quartz blank. The interconnection via process for wafer level crystal unit package with 2.0×1.6×0.45 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> size and results of electrical performance is evaluated.

Some of the critical issues of wafer level chip scale package (WLCSP) are discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the important parameters such as wafer-level redistribution, wafer bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layers on the solder joint reliability of WLCSP on printed circuit boards (PCB) through creep responses such as deformation, hysteresis loops, and stress and strain are presented. Only solder-bumped WLCSPs with pad-redistribution are considered in this study.

As electronic devices decrease in size and increase in functionality, their surface-mount components grow in number. This trend created a need for securing appropriate space in and on a wiring board to accommodate necessary components. Conventionally, dies are mounted on a wiring board. Much effort is spent for space savings. We have come up with a structure to include dies inside a wiring board and succeeded in fabricating the board in which two dies are embedded in a 3D stacked configuration. This new structure shrinks the foot print size and thus contributes to higher density and functionality of a semiconductor package and SiP. In addition, since the base material is polyimide, this board is as thin as 0.45 mm with two WLP (Wafer Level Package) dies (3 mm x 3 mm x 0.085 mm) embedded between any of 9 wiring layers. The module level warpage on the both sides of this board is 0.035 mm, so it is possible to mount components on the both sides. This board was fabricated based on our WABE technologyTM (Wafer and Board level Embedding technology) that includes a single step co-laminating process and embedded technology using conductive-paste-filled vias for establishing z-axis interlayer electrical connections. The conductive paste formed intermetallic compound with the copper foil and the via showed stable electrical connections by metallic bonding. Copper pads were fabricated on the dies by a wafer level process in advance. The polyimide-based films were laminated with adhesive and the dies were embedded. At the same time, electrical connections were established. This method enables the production of an embedded board by one-time curing after the alignment and fixing of necessary layers. We applied this method to the new structure that includes two dies in a 3D configuration to achieve a simple fabrication process using the single step co-lamination process. We evaluated the reliability of this board as below. The electric resistance was measured after various reliability tests including Temperature Cycle Test, Temperature Humidity Bias Test and Highly Accelerated Stress Test following a moisture sensitive reflow test (based on IPC/JEDEC J-STD-020 Level 3). From the results, there were no major defects observed in the test boards, either visually or functionally. This two-die embedding technology helps to realize the miniaturization and contribute to higher functionality of semiconductor packages and SiPs.

Over the past few years, Wafer Level Chip Size Packages (WLCSPs) have gained widespread adoption, due to their ability to deliver higher performance at lower or equivalent costs when compared to competing packages. WLCSPs have been an excellent fit for the handheld/portable industry, where the strong push for cost-reduction and miniaturization, coupled with relatively relaxed reliability requirements, have motivated true chip-sized packages requiring no underfill or overmold. Reliability performance initially limited the application of WLCSPs to small die sizes (&amp;lt;2.5mm), low pin counts (&amp;lt;25) and mature silicon technology nodes. Also, to date, a majority of WLCSPs have been built at a 0.5mm bump pitch, although there is increasing growth in the use of WLCSPs at 0.4mm pitch. These factors have allowed WLCSP packaging to flourish in the mixed signal and analog market space. With the maturity in this market segment, the WLCSP is beginning to transition from an advanced package to a commodity package and is subject to the price-pressure that accompanies this transition. More recently, the semiconductor industry has seen advances in WLCSP technology which have enabled the qualification envelope to be expanded to products with pin counts &amp;gt; 120. These advances have facilitated the use of WLCSPs for other component types such as RF, high speed, broadband and memory, many of which require advanced silicon technology nodes as well. Consequently, WLCSP is expanding to markets and applications previously supported by QFN and flip chip CSP. This expansion puts additional price and cycle time pressure on WLCSP manufacturing. The cycle time pressure is further enhanced by the changing business models and supply chain strategies adopted by companies in the new economic environment. To meet these growing market demands, WLCSP providers are faced with the challenges of providing faster cycle times and higher capacity without significant increases in capital expenditure. The above factors have driven the need for new WLCSP technologies that utilize fewer process steps compared to common WLCSP product offerings, while maintaining the robustness necessary for meeting quality and reliability requirements. Amkor is developing multiple WLCSP technology platforms to cater to the cost and performance requirements of the diverse application space. This paper will provide examples that significantly reduce overall package cost by removing photolithography layers. Each photomask layer removed saves in material costs, capital depreciation costs, overhead, and process cycle time. Materials, package size, and internal qualification vehicles are carefully chosen as part of Amkor's product introduction for the proposed process flows. This paper will examine material options, i.e., polymers and solder alloys, for these new structures and will also examine the effects of die sizes and I/O counts on product reliability. Detailed analyses of the failure modes produced during reliability testing will be coupled with mechanical simulations to enhance understanding of the failure mechanisms and to further strategies for improving product reliability.

Wafer Level Packaging (WLP) has started to shine and played a prominent role in recent years in both semiconductor and Integrated Circuit (IC) field, especially in now thriving Micro-Electro-Mechanical System (MEMS) applications on account of its distinctive operating mechanism and adaptive design variety. In this study, several crucial WLP technologies are disclosed in detail, including Wafer to Wafer (W2W) bonding, wafer level wire bonding, wafer level compound molding and lapping. Simplified and conceptual process flow of MEMS WLP and development approaches are introduced and explained. Furthermore, relevant experimental results and technology characteristics, including glass frit printing and bonding results & shear strength in W2W bonding technology, wire shift & vertical loop height & ball shear & wire pull in wafer level wire bonding technology, Thickness to Thickness Variation (TTV) & wire sweep & warpage in wafer level compound molding technology, have also been extensively demonstrated. After MEMS WLP packaging process, device performance is then determined by the difference of voltage readout with the implementation of Wafer Level Dynamic Test (WLDT) before and after Highly Accelerated Stress Test (HAST), and the wafer device yield is also presented.

A low-cost, highly reliable UFI (UBM-free integration) wafer level chip scale packaging (WLCSP) for high performance, large die (>100 mm2) with fine solder ball pitch (350 µm) and high I/O (>800) has been developed. Reliability issues including solder cracking and high chip warpage are known to be the main challenges for extending the die size of conventional WLCSP to more than 5x5 mm2 with ball pitch smaller than 350 µm. In this paper, we present the novel WLCSP designed with a stress-mitigation structure which can significantly enhance the reliability of the package and enables die size extension. By controlling the maximum strain location and optimizing the materials using the stress-mitigation structure, the chip warpage and the stress between Si and PCB can be effectively reduced to enhance both component and board-level reliabilities of the package. The UFI WLCSP passed all component-level tests and exhibited board-level thermal cycle life that is 1.4 and 2.3 times longer than that of the conventional WLCSP in terms of the first failure and the Weibull distribution (t63), respectively. As a result, highly reliable packages with various die sizes, including 5.2x5.2, 7.2x7.2 and 10.3x10.3 mm2 and with both 400 and 350 µm ball pitches have been developed. The RDL within the package of UFI WLCSP can be utilized to form inductor structure which exhibits quality-factor nearly 50% higher than that of an on-chip inductor. Besides, in WLCSP process, die sawing typically causes delamination and cracking of packages which results in process failure in the WLCSP. The UFI unique structure consists of sidewall protection which is capable of preventing chipping and therefore effectively improves the process controls and the reliability margins. In addition, to fulfill the requirement of high I/O products and to enhance the design flexibility, we embedded multiple RDL in UFI WLCSP with die size of 10.3x10.3 mm2 and ball pitch of 350 µm, which provides a fan-in package solution with I/O >800. The large die UFI WLCSP has passed the component-level reliability tests of TCB1000, uHAST96 and HTS1000, and board-level reliability tests of TCG500 and drop tests.

Wafer-Level Chip Scale Packages (WLCSPs) are becoming commonplace in the industry due to their small form factor. Applications include industrial and automotive which demand high reliability performance. Additionally, WLCSPs may be superior in some implementations to other package options for RF performance in the mmWave spectrum, which is desired for automotive radar application. But board level reliability can be a challenge for some WLCSP package due to CTE mismatch between Si and PCB. Variety of factors including PCB materials, sphere alloys, and board level underfills can influence the board level reliability of WLCSP packages. In this study the industry’s first auto grade 1 capable large WLCSP package. (~ 72 mm 2 body size, 18×15 BGA array, 0.5 mm pitch) is presented. Board level underfill application was utilized to achieve automotive grade board level reliability. Underfills are typically selected based on thermomechanical properties of unaged materials. An understanding of the evolution of underfill material properties under thermal aging is important for selecting a stable material capable of meeting the reliability requirements. This study evaluates board level underfills and edge bond materials in the form of stand-alone samples and applied to a large daisy-chain WLCSP. The underfilled daisy-chain WLCSPs and the stand-alone samples are placed in a -40/125C air cycling chamber (1 cycle/hour). Glass transition temperature (Tg), elastic modulus (E), and coefficient of thermal expansion (CTE) are measured using Dynamic Mechanical Analysis (DMA) and Thermomechanical Analysis (TMA) on the stand-alone samples at various intervals to monitor the evolution of material properties. Simultaneously, the underfilled daisy chain WLCSPs are monitored electrically using an event detector. The combination of material property measurements and cycles to electrical failure can be used to correlate underfill material properties and WLCSP board-level reliability. The results of this study can provide material property guidance for underfill selection.

This work focuses on the development of Integrated Passive Devices (IPD) from electrical design, modeling and simulation till final fabrication and device technology qualification stage. Passivation layer of Polyimide (PI) type was used as inter-metal dielectric materials together with semi-additive copper plated redistribution layer (RDL) as conductive material that carries signal traces through the devices. It also applies multilayer thin film technology used in Wafer-level Packaging (WLP) processes. The thin film setup was designed at 6-layers, which comprises three Polyimide layers and three RDL. Passive devices are designed for Radio Frequency Integrated Circuit (RFIC) applications that work mainly at frequencies of 2.4GHz and 5GHz. For IPD, inductors cover the range of InH and 23nH, and capacitors are within range of 0.03pF to 2.5pF. Several coplanar waveguide (CPW) transmission line structures were also included in the test vehicle prototype to characterize the copper RDL quality in transmitting high-frequency signals at Gigahertz range. Substrate material of low resistivity silicon wafers at 25 Ohm.cm was used for these structures which influences the quality factor of coils and capacitors. Integrated inductors and capacitors structures with stack-up of passivation and copper RDL were designed at realistic Wafer-level thin film thickness, which allows robust integration into WLP platform. Structures correlation of high-frequency measurements and simulation showed maximum of 5% deviation at high-frequency bandwidth. Fabricated structures perform well in time-zero failure analysis and reliability test of High Temperature Storage (HTS 500hr).

Ball Grid Array (BGA) packages with 1.27 mm pitch arrays are now being extended to fine pitch BGAs, or Chip Scale Packages (CSP) with ball diameters of 0.3 mm and array pitches as small as 0.5 mm. The current work analyzes the impact of integrating such packages into a high volume SMT assembly line and examines the impact of process and board variables on the reliability of the total assembly. The CSP chosen for the current study was a 0.75 mm pitch CSP scheduled to replace the 0.5 mm lead pitch Thin Small Outline Package (TSOP) currently used in high volume, small form factor, flash memory products. The CSP dimensions of approximately 5.6 mm by 7.4 mm represents an 80% reduction in package area compared to the traditional TSOP, with a footprint of 12 mm by 20 mm. The study examines the effect of solder paste printing parameters, flux-only assembly, and printed circuit board surface finishes such as immersion gold and solder-leveling. Solder paste volume measurements were made on over 2800 individual CSP pads during the builds using an in-line, automated laser scanning profilometer. Reliability test vehicles were assembled using CSPs, TSOPs and other surface mount components, prior to performing accelerated thermal cycling tests from 0/spl deg/C to 100/spl deg/C, and 40/spl deg/C to 85/spl deg/C. CSP placements were performed using optimized high speed chip placers to place CSPs at rates of up to 5 parts per second. Interim reliability test results after four months of testing are presented with a discussion of TSOP versus MicroBGA package construction.

Semiconductors are currently connected to other system components by three main interconnect technologies: wirebond, TAB and solder bump. These processes are significant contributors to the cost of the bumped wafer. In the packaging industry, there is also a drive for towards wafer level packaging solutions in order to minimize the packaging cost and give high production rates. This paper describes the development of a new wafer level process which minimizes the cost of the bumped wafer that requires bond pad redistribution, and at the same time offers the advantages of a wafer level packaging solution. The process is based on the concept of a build up technology that channels the bond pads to a large pitch array in order to make the interconnection to the board. The packaging technology is suited to high frequency, small size, lightweight applications. This process has the potential to drive the industry away from wire bonding to a single step wafer level interconnection process. The paper also provides the results of the characterization that was performed on the package.

Wafer level CSP (WLCSP) has been paid great attention due to its miniature size. It is a real chip size package from the package perspective. It is also a known good encapsulated die (KGED) from the die perspective. This means that the boundary between package and bare die becomes indistinct. It sometimes referred to as a 'packageless' package. It is no longer meaningless to enquire whether CSP or bare die should be used since WLCSP is emerging. WLCSP is shaped by wafer level packaging (WLP) and wafer level testing (WLT). At this time, eight WLCSPs are proposed using different kinds of WLP. Three WLT are also proposed, including the authors' own technology. We developed the Super CSP/sup TM/ using a unique WLP with five major processes: re-routing, metal-post forming, compression moulding, solder ball placing and dicing. This package allows a system designer to layout a motherboard at the smallest area possible. It also allows an assembly engineer to mount on a motherboard and replace from the motherboard similar to conventional CSPs, and allows a test engineer to test and burn-in much more easily than with known good die (KGD). We confirmed excellent electrical performance, package reliability, mountability, and second level packaging reliability.

Heterogeneous integration for system in package (SiP), flip-chip integration in 3D packaging and embedded ICs in advanced Printed Circuit Boards (PCB) are all pushing the limits for low profile packaging. Advanced polymer materials applied in Semiconductor-on-Polymer™ wafer level chip scale packaging (SoP WLCSP) are gaining traction as a high reliability ultra-thin packaging solution. The 2019 roadmap for Heterogeneous Integration defines heterogeneous Integration (HI) as the integration of separately manufactured components into a higher-level assembly that provides enhanced functionality and improved operating characteristics. The development of this technology is a significant industry challenge that can evolve quickly with the application of SoP polymer based packaging. At advanced nodes, die yield falls exponentially with die size. Splitting a large monolithic SoC into smaller tightly coupled die, is an attractive alternative considering that die cost per unit area is escalating. The smartphone industry has been an early adopter of HI technologies in the use of SiP for multiple generations, essentially for the advantages in miniaturization, modularity for co-design, and enhanced generation-over-generation performance. The application processor is almost always on the most advanced node and housed in a Package on Package (PoP) configuration with memory component(s) stacked on top of this ASIC. Teardowns of the Package-on-Package (PoP) packages for Apple XSMax, Samsung Galaxy S9+, and Huawei 20 Pro have shown the utilization and need for continued z-axis thickness scaling. Implementation of SoP CSP for package in package integration or for chip on thin PCB, interposer or flex can provide another package capability for evolution of multi-layer heterogeneous integration. Reliable ultra-thin polymerized die have the potential to tackle the third dimension (z-axis) of total IC package volume in 3D integration. SoP die can replace current full thickness or partially thinned (typically &gt;250µm) die with &lt;35µm package thickness devices. In addition, the SoP process has the potential to extend package roadmaps enabling smaller higher performance packages in several areas, including Fan-Out (FO). Thin bridge die could simplify localized high IO for substrates. Thin embedded IPD (integrated passive devices) have the potential to increase the capability and shrink the size of substrate process based passives, similar to the performance increase for wafer based devices versus printed electronics. In addition thin high IO die could allow simplified embedding in substrates. The differentiation of PCBs, interposers and flex circuits is starting to blur. Package integration within the layers of these devices can create embedded ICs that take less system space and improve system performance. Traditionally, manufacturing steps to place an IC within the board substrate vary and require space to be created for the component body, in the form of a cavity for traditional packaged ICs. In Integrated module board (IMB), components are aligned and placed inside a cavity that is routed to the core laminate by controlled-depth routing. The cavity is filled with molding polymer to ensure chemical, mechanical, and electrical compatibility with the substrate. Isotropic solder is impregnated with the polymer to form reliable solder joints when the embedded part is laminated into the stack. Polymerized ICs in SoP CSP eliminate cavity requirements and molding polymers for IMB. Chip in polymer (CIP) approaches use thin chips in built up dielectric layers of PCBs, rather than integrating them into the core layers. When SoP CSP is applied, it is feasible to achieve the same capability, but with a much smaller z-axis and without creating a surface geography perturbation. This presentation will include an introduction to SoP CSP utilizing advanced polymer technology for accelerating evolution of HI, PoP and Embedded applications.