Glitch Resistant Private Circuits Design Using HORNS

Hardware implementations of cryptographic algorithms are still vulnerable to side-channel attacks. Side-channel attacks that are based on multiple measurements of the same operation can be countered by employing masking techniques. In the presence of glitches, most of the currently known masking techniques still leak information during the computation of non-linear functions. We discuss a recently introduced masking method which is based on secret sharing and results in implementations that are provable resistant against first-order side-channel attacks, even in the presence of glitches. We reduce the hardware requirements of this method and show how to derive provable secure implementations of some non-linear building blocks for cryptographic algorithms. Finally, we provide a provable secure implementation of the block cipher Noekeon and verify the results.

Side channel attacks have received much attention as of recent. Compared with cryptanalysis that focus on the algorithms themselves, side channel attacks are usually much more practical and realistic. Side channel attack is closely related to hardware and implementations. Many cryptographic algorithms that are secure by themselves become insecure when they are poorly implemented or are running on devices with special properties. In this work, we examine the probability of side channel attacks on phase change memory which is envisioned as a candidate of universal memory to replace DRAM or SRAM. The attacks exploit the seasoning effect of phase change memory, a phenomenon of PCM cell behavior change as a function of operative cycles. We conducted detailed experiments using PCM modeling tools that accurately simulate the seasoning effect of PCM cells. The results show that for pipelined AES cipher that is not properly implemented when using PCM as the storage device, side channel attacks may lead to serious security risks. We also provide suggestions for secure implementation of AES to prevent such attacks.

Quantum Cryptography for Internet of Things Security

Side-channel attacks bypass the theoretical strength of cryptographic algorithms by exploiting weaknesses in the cryptographic system hardware implementation via nonprimary, side-channel inputs and outputs. Commonly exploited side-channel outputs include: power consumption, electromagnetic (EM) emissions, light, timing, and sound (Fig. 8.1). Commonly used side-channel inputs include: supply voltage, temperature, light, and other primary signal inputs unrelated to the cryptographic block. The attacks themselves combine observation of side-channel outputs, manipulation of side-channel inputs, observation of primary outputs, and manipulation of primary inputs with increasingly complex analysis techniques to discover secret information from the cryptographic system. Attacks that exploit side-channel output are often termed passive side-channel attacks, while attacks that exploit sidechannel inputs are called active side-channel attacks or fault injection attacks.

The role of the side channels in the continuous-variable quantum key distribution is studied. It is shown how the information leakage through a side channel from the trusted sender station increases the vulnerability of the protocols to the eavesdropping in the main quantum communication channel. Moreover, the untrusted noise infusion by an eavesdropper on the trusted receiving side breaks the security even for a purely attenuating main quantum channel. As a method to compensate for the effect of the side-channel leakage on the sender side, we suggest several types of manipulations on the side-channel input. It is shown that by applying the modulated coherent light on the input of the side channel that is optimally correlated to the modulation on the main signal and optionally, introducing additional squeezing in the case of the squeezed-state protocol, the negative influence of the lossy side channel on the sender side can be completely removed. For the trusted receiving side, the method of optimal monitoring of the residual noise from the side-channel noise infusion is suggested and shown to be able to completely eliminate the presence of the noisy side channel. We therefore prove that the side-channel effects can be completely removed using feasible operations if the trusted parties access the respective parts of the side channels.

Side channel attacks are based on side channel information, which is information that is leaked from encryption systems. Implementing side channel attacks is possible if and only if an attacker has access to a cryptosystem (victim) or can interact with cryptosystem remotely to compute time statistics of information that collected from targeted system. Cache timing attack is a special type of side channel attack. Here, timing information caused by cache effect is collected and analyzed by an attacker to guess sensitive information such as encryption key or plaintext. Cache timing attack against AES was known theoretically until Bernstein carry out a real implementation of the attack. Fortunately, this attack can be a success only by exploiting bad implementation in software or hardware, not for algorithm structure weaknesses, and that means attack could be prevented if proper implementation has been used. For that reason, modification in software and hardware has been proposed as countermeasures. This paper reviews the technique applied in this attack, surveys the countermeasures against it, and evaluates the feasibility and usability of each countermeasure. We made comparison between these countermeasure based on certain aspect furthermore.

The design of digital systems has its mainstay in the electronic design automation flows which act as crucial instruments to reduce the effort to realize complex computing platforms. In this work, we investigate the possibility of integrating side channel security analyses within the existing FPGA design flow, to provide a feedback to the hardware designer in a prompt and effective way. To this end, we realize an analysis framework which detects side channel leakage on the power consumption side channel at two well established checkpoints in hardware design, i.e., post synthesis and post implementation. We report the results of the proposed framework when integrated within the commercial Xilinx Vivado design toolchain. As a case study, we employ an open source SoC running a software version of the AES block cipher and provide a taxonomy of the side channel information leakage. The reported results highlight how our approach is able to provide precise insights on the sources of information leakage in the hardware design at hand. In particular, we show that the results of the simulations at post synthesis and post implementation stages provide complementary sets of insights on the information leakage, which, thanks to our methodology, can be traced back to architectural components which are the culprits of the said leakage.KeywordsDesign automation and toolsFPGA design flowSide channel analysis

The goal of this paper is to answer how much information is “transmitted” by the execution of particular sequence of instructions in a processor. Introducing such a measure would provide quantitative guidance for designing programs and computer hardware that minimizes inadvertent (side channel) information leakage, and would also help detect parts of a program or hardware design that have unusually high leakage (i.e., were designed to function as covert channel “transmitters”). To answer this question, we propose a new method to estimate the maximum information leakage through EM signals generated by the execution of instructions in a processor. We start by deriving a mathematical relationship between electromagnetic side-channel energy of individual instructions and the measured pairwise side-channel signal power. Then, we use this measure to calculate the transition probabilities needed for estimating capacity. Finally, we propose a new method to estimate side/covert channel capacity created by the execution of instructions in a processor and illustrate our results in several computer systems.

The side channel attack (SCA) is a serious attack on wearable devices that have scarce computational resources. Cryptographic algorithms on them should be efficient using small memory — we have to make efforts to optimize the trade-off between efficiency and memory. In this paper we present efficient SCA-resistant scalar multiplications based on window method. Möller proposed an SPA-resistant window method based on 2 w -ary window method, which replaces w-consecutive zeros to 1 plus w-consecutive 1 and it requires 2 w points of table (or 2w-1 +1 points if the signed 2 w -ary is used). The most efficient window method with small memory is the width-w NAF, which requires 2w-2 points of table. In this paper we convert the width-w NAF to an SPA-resistant addition chain. Indeed we generate a scalar sequence with the fixed pattern, e.g. 0..0x0..0x...0..0x, where x is positive odd points < 2w. Thus the size of the table is 2w-1, which is optimal in the construction of the SPA-resistant chain based on width-w NAF. The table sizes of the proposed scheme are 6% to 50% smaller than those of Möller’s scheme for w = 2, 3, 4, 5, which are relevant choices in the sense of efficiency for 160-bit ECC.

Side channel attacks recover keys or other sensitive information by using the time, power consumption, electromagnetic radiation and fault output generated when cryptographic algorithms are executed on IOT devices. It has become one of the important threats to cryptographic security devices. In recent years, deep learning technology is widely used in the field of Side Channel Attack (SCA). In this paper, a side channel attack method based on deep learning Long Short-Term Memory (LSTM) is proposed. Because of the interpretability of the internal nonlinear structure of LSTM, its system identification capability and computational complexity are superior to those of deep learning network. To test the effectiveness of the modified attack method, we evaluated it using a public ASCAD dataset. We conducted a side-channel analysis experiment for the AES-128 encryption algorithm. Experimental results show that this method achieves good attack effect and effectively alleviates the influence caused by trajectory misalignment. The interest points of the side channel power data are determined by using the correlation power analysis method, and the appropriate interest intervals are selected as feature vectors to build the neural network model. The experimental results show that compared with MLP and CNN models, LSTM network model has higher attack efficiency in side channel attack.KeywordsSide channel attackLong short-term memoryDeep learning

We propose a data-driven method for synthesizing static analyses to detect side-channel information leaks in cryptographic software. Compared to the conventional way of manually crafting such static analyzers, which can be tedious, error prone and suboptimal, our learning-based technique is not only automated but also provably sound. Our analyzer consists of a set of type-inference rules learned from the training data, i.e., example code snippets annotated with the ground truth. Internally, we use syntax-guided synthesis (SyGuS) to generate new recursive features and decision tree learning (DTL) to generate analysis rules based on these features. We guarantee soundness by proving each learned analysis rule via a technique called query containment checking. We have implemented our technique in the LLVM compiler and used it to detect power side channels in C programs that implement cryptographic protocols. Our results show that, in addition to being automated and provably sound during synthesis, our analyzer can achieve the same empirical accuracy as two state-of-the-art, manually-crafted analyzers while being 300X and 900X faster, respectively.

Cyber-attacks stealing confidential information are becoming increasingly frequent and devastating as modern software systems store and manipulate greater amounts of sensitive data. Leaking information about private user data, such as the financial and medical records of individuals, trade secrets of companies and military secrets of states can have drastic consequences. Confidentiality of such private data is critical for users of these systems. Many software development practices, such as the encryption of packages sent over a network, aim to protect the confidentiality of private data by ensuring that an observer is unable to learn anything meaningful about a program’s secret input from its public output. Under these protections, the software system’s main communication channels, such as the content of the network packets it sends, or the output it writes to a public file, should not leak information about the private data. However, many software systems still contain serious security vulnerabilities. Side channels are an important class of information leaks where secret information can be captured through the observation of non-functional side effects of software systems. Potential side channels include those in execution time, memory usage, size and timings of network packets, and power consumption. Although side-channel vulnerabilities due to hardware (such as vulnerabilities that exploit the cache behavior) have been extensively studied [1] , [2] , [10] , [13] , [15] – [17] , [19] , [23] , software side channels have only recently become an active area of research, including recent results on software side-channel detection [4] , [8] , [11] , [12] , [18] , [22] , [24] and quantification [5] , [20] , [21] , and my own work on a static analysis framework for detection of software side-channels called CoCo-Channel [8] ) and a constraint caching framework to accelerate side-channel quantification called Cashew [9] .

Side channel attacks (SCAs) exploit the fact that security IC physical implementation of a cryptographic algorithm can leak information of the secret key. One of the most important SCA is Differential Power Analysis (DPA), that uses the power consumption dependence with the data processed to reveal critical information. To protect security devices against this issue, differential logic styles with constant power dissipation have been widely used. However, the right use of such circuits for secure applications needs not only a fully symmetric structure, but also removing any memory effect that could leak information. We propose an improved memory-less fully symmetric Xor/Xnor pull-down logic configuration, to be used with any differential technique, for immediate application in crypto-graphic secure applications.

&lt;p&gt;Cryptographic algorithms need infrastructure for testing them against security attacks. Normally many methods are proposed for testing these cryptographic primitives. Normal designs cannot be applied to all types of cryptographic chips. Usually build in self test is applied for the intellectual property chips for testing them. But it suffers from many problems such as side channel attack, backholes, high area overhead, etc.., to overcome all these drawbacks test wrapper is designed and tested using NIOS II economy soft core processor. NIOS II is utilized as the soft core processor and cryptographic algorithms are executed. RTL view of these cryptographic circuits is described. Synthesis result shows the chip planner view of the circuits and the area required for the logic elements. NIOS II soft-core processors perform well for testing the cryptographic algorithms. Results with respects to area optimization, memory and speed are discussed. The logic components required for design using NIOS II is optimized. Memory required is also less compare to other processors. Area required is optimized using NIOS II processor and it is flexible for design of complex circuits.&lt;/p&gt;

The RSA cryptographic algorithm is a security tool that has achieved long cryptographic and market maturity. However, after the discovery and wide spread of Side Channel Attacks (SCA), RSA implementations are susceptible to a variety of different attacks that target the hardware structure rather than the algorithm itself. While there are a wide range of countermeasures that can be applied on the RSA structure in order to protect the algorithm from specific SCA categories, combining several such measures to produce an "all in one" SCA resistant RSA structure is not an easy endeavor. Several incompatibility issues between combined SCA protection methods lead to new SCA vulnerabilities. In this paper, we evaluate some very popular and potent SCAs against RSA, like Fault attacks (FA), Simple Power attacks (SPA), Doubling attacks (DA) and Differential Power attacks (DPA), and propose an SCA protection scheme for RSA based on Chinese Remainder Theorem (CRT) that can thwart them. The proposed scheme uses a square and always multiply approach in combination with the message blinding technique in such a way that possible vulnerabilities that may rise from this combination can no longer apply. The proposed scheme is evaluated against specific SCAs and is found to be very secure. From performance point of view, the proposed scheme favors parallelism and can calculate an RSA result with small time delay.