Global operations in SIMD cellular processor arrays employing functional asynchronism

A class of fine-grained (FG) parallel models and algorithms is defined as a generalization of Cellular Automata (CA). It comprises all CA-modifications, in which two main CA-properties (locality and parallelism of intercell interaction) are preserved, no constraint being imposed on state alphabets and transition functions. A set of methods for composing a complex FG-algorithm out of a number of simple ones is proposed. To make compatible FG-algorithms with different alphabets, a number of algebraic operations on cellular arrays are introduced. The set of proposed composition methods has a two-level structure: the lower level comprises composition of cell transition functions, while the higher level deals with global operators on cellular arrays. For each type of proposed methods an example is given and the domain of application is determined.

The real-time implementation of a dynamic-time-warping (DTW)-based isolated-word recognizer on the general-purpose, cellular array processor (CAP) chip ACIIM is described. In this implementation a single CAP performs both the preprocessing and the DTW computations. The front end is based on a parallel filter bank. The DTW computation proceeds on a diagonal basis, each diagonal being computed by the array of 16 processors contained in the CAP. The time needed for a diagonal computation is 10.5 mu s. with a pipelined structure in the reference templates more than 800 DTW comparisons can be computed in 600 ms, assuming an average word duration of 0.8 s.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Unmanned Arial Vehicles (UAVs) require the development of some on-board safety equipments before inheriting the sky. An on-board collision avoidance system is being built by our team. Due to the strict size, weight, power, and costs constraints, visual intruder airplane detection is the only option. This paper introduces our visual airplane detector algorithm, which is designed to be operational in clear and in cloudy situations under regular daylight visual conditions. To be able to implement the algorithm on-board, we have carefully selected topographic operators, which can be efficiently solved on cellular processor arrays.

This paper demonstrates an implementation of an asynchronous cellular processor array that facilitates binary trigger‐wave propagations, extensively used in various image‐processing algorithms. The circuit operates in a continuous‐time mode, achieving high operational performance and low‐power consumption. An integrated circuit with proof‐of‐concept array of 24×60 cells has been fabricated in a 0.35µm three‐metal CMOS process and tested. Occupying only 16×8µm2the binary wave‐propagation cell is designed to be used as a co‐processor in general‐purpose processor‐per‐pixel arrays intended for focal‐plane image processing. The results of global operations such as object reconstruction and hole filling are presented. Copyright © 2010 John Wiley &amp; Sons, Ltd.

A software tool for the development, prototyping and emulation of cellular processor array hardware is presented. APRON provides a dasiavirtual processor arraypsila that operates at high speed, that can be extended to form vision systems, multi-layer neural networks, cellular neural networks and neuromorphic arrays.

This paper presents an FPGA realisation of an application-specific cellular processor array designed for asynchronous skeletonization of binary images. The skeletonization algorithm is based on ite...

A prototype vision chip has been designed that incorporates a 20 × 64 array of processing elements on a 31μm pitch. Each processor element includes 14 bits of digital memory in addition to 7 analogue registers. Digital operands include NOR and NOT with operations of diffusion, subtraction, inversion and squaring available in the analogue domain. The cells of the array can be configured as an asynchronous propagation network allowing operations such as flood filling to occur with times of ~1μs across the array. Exploiting this feature allows the chip to recognise the difference between closed and open shapes at 30,000 frames per second. The chip is fabricated in 0.18μm CMOS technology.

In this chapter, the architecture, design and implementation of a vision chip with general-purpose programmable pixel-parallel cellular processor array, operating in single instruction multiple data (SIMD) mode is presented. The SIMD concurrent processor architecture is ideally suited to implementing low-level image processing algorithms. The datapath components (registers, I/O, arithmetic unit) of the processing elements of the array are built using switched-current circuits. The combination of a straightforward SIMD programming model, with digital microprocessor-like control and analogue datapath, produces an easy-to-use, flexible system, with high-degree of programmability, and efficient, low-power, small-footprint, circuit implementation. The SCAMP-3 chip integrates 128 ×128 pixel-processors and a flexible read-out circuitry, while the control system is fully digital, and currently implemented off-chip. The device implements low-level image processing algorithms on the focal plane, with a peak performance of more than 20 GOPS, and power consumption below 240mW.

The design of a high-speed cellular pattern matcher, called theAssociative Linear Text Processor (ALTEP), is presented.ALTEP was originally designed for systems which use signature files as an access method. However, it is also suitable for systems which store the database in fixed length blocks.ALTEP is a linear array of logic cells which respond to commands sent from a central controller over a bus. A text block is loaded into the cells and pattern characters are broadcast to the cells for comparison.ALTEP has the capability of recognizing full regular expressions and is the only cellular logic array which has this capability. It requiresO(p) steps for patterns which do not contain closures andO(len(max(T(P)))) steps for closures, wherep is the the length of the pattern andlen(max(T(P))) is the length of the longest substring in the text which matched the closure.

Comparison of 2-D gel electrophoresis images

Behavioral Simulation of Densely-Connected Analog Cellular Array Processors for High-Performance Computing

The cellular iterative computation model bears upon three broad-ranging application domains: pixel-level image processing, finite-difference approximation of continuum problems (boundary value PDEs) in computational physics, and cellular automata as discrete models of complex locally-interacting systems, aimed at probing their emergent collective properties. The common underlying idea is to compute the global dynamics of a lattice-structured state-space through the iterative propagation of purely local computational dependencies between state-components. A past generation of mesh-connected SIMD array-processors, among which the MPP [Bat 80], CLIP [Pre 84] and CAM [Tof 87] machines, were canonical architectural mappings of this fruitful concept. All were fine-grain synchronous solutions. The new generation of MIMD RISC-based parallel computers that superseded them are essentially coarse-grain and asynchronous; They can simulate a cellular iterative model in a parallel pseudo-synchronous SPMD mode with global coordination mechanisms. A fine-grain asynchronous architectural model departs in a somewhat paradoxical way from these two mainstream approaches. The idea is to match an architecture with a functional concept of a synchronism, specific to cellular relaxation algorithms. As we show in the following, benefits accrue at both levels from this matching.

This paper reviews the ever increasing activity in smart sensors, initiated in the 80’s by Mead’s silicon retina design. The gap between the sensors and the processors in a traditional image processing system can be partially reduced by embedding into the same silicon die both the transduction of incoming illumination and its interpretation through some processing function. If we consider the silicon die a “real estate” on which to build the smart sensor, many possible alternatives arise, which either privilege the sensing function or the processing one. On-chip-vision is the domain of integration that tries to balance the available silicon resources between these two extreme approaches. Analog processing is a viable solution for many tasks, though it leads to implementations that lack a general programmability. Application specific solutions, according to the ASIC paradigm, take a more flexible approach in mixing both analog and digital processing, according to the single task embedded in the silicon die. General purpose digital retinas, which combine an array of sensors with a programmable digital cellular array of simple processors, have also been proposed and built; the area trade-off between the sensing function and the near-neighbour connectivity suited to low level image processing is a major issue for further research.

An SIMD cellular array processor “AAP2” and its programming language AAPL have been developed. This array processor is packed into as little as 0.2 m volume in spite of its massive processor array being composed of 256 × 256 single‐bit processing elements [PEs], each of which has 8‐kbit local memory. The compact size is due to the simple and regular array structure for dense packing and a custom CMOS LSI with 8 × 8 PEs developed for the processor array.The massive processor array offers outstanding operation power together with the following functions: (1) modified SIMD control which is able to select a different operation function or different direction of inter‐PE transfer in each PE; (2) propagation transfer operation capable of propagating data through 15 PEs within one clock cycle (330 ns).The AAPL enables a simple and efficient program to be designed due to its APL‐like scanning statements and its primitive operation statements for unique AAP functions.The high performance of the AAP2 has been shown to be equivalent in simulation capability to the very high‐speed hardware logic simul.ator or routing capability of over 1000 MIPS in the automatic chip layout design.

Fast parallel processing of gray-scale images and exact hard-clip thresholding are two important functionalities necessary in optoelectronic implementations of structural processors. The parallel nature of processing stems from optical implementation of local operations with arrays of active smart pixels. We have demonstrated a morphological image processor composed of arrays of bistable optoelectronic transceivers which are connected in differential pairs and work as comparators. The use of differential pairs of optical thyristors fabricated in GaAs technology allows to realize a dual rail architecture for this photonic morphological image processor. The processor consists of a thresholding module and a binary morphological processing module. The thresholding module decomposes gray level images into series of binary slices. In the binary morphological processing module operations are performed within a neighborhood defined by a structuring element implemented as a diffractive fan-out element. In the prototype set-up we demonstrate median filtering, dilation and erosion operations performed for an image of 8x8 pixels and threshold decomposition of 6 gray level images. In principle all rank order as well as morphological filters can be optically calculated in the set-up. Additional functionality of the processor is achieved with use of the electronic layer with digital cellular processors. The electronic layer, designed as an array of simple digital processors, realizes a set of operations on binary images using 4 bit programmable weights. Simulation results for 0.8 µm CMOS technology are presented. We discuss the limitations of the photonic morphological image processing with respect to bandwidth, parallelism and architecture of the processor.