GOP-level parallelization of the H.264 decoder without a start-code scanner

Work-stealing is a popular method for load-balancing dynamic multithreaded computations on shared-memory systems. In theory, a randomized work-stealing scheduler can achieve near linear speedup when the computation has sufficient parallelism and requires stack space that is linear in the number of processors. In practice, however, work-stealing runtimes sacrifice interoperability with serial code to achieve these bounds. For example, both Cilk and Cilk++ prohibit a C function from calling aCilk function. Other work-stealing runtime systems that do not have this restriction either lack a strong time bound, which might cause them to deliver little or no speedup in the worst case, or lack a strong space bound, which might lead to an excessive memory footprint. This problem was previously described as the cactus stack problem.

We consider the problem of energy-efficient scheduling for slice-parallel video decoders on multicore systems with Dynamic Voltage Frequency Scaling (DVFS) enabled processors. We rigorously formulate the problem as a Markov decision process (MDP), which simultaneously considers the on-line scheduling and per-core DVFS capabilities; the power consumption of the processor cores and caches; and the loss tolerant and dynamic nature of the video decoder. The objective is to minimize long-term power consumption subject to a minimum Quality of Service (QoS) constraint related to the decoder’s throughput. We evaluate the proposed scheduling algorithm using traces generated from a cycle-accurate multiprocessor ARM simulator.

Counting the abundance of all the distinct kmers in biological sequence data is a fundamental step in bioinformatics. These applications include de novo genome assembly, error correction, etc. With the development of sequencing technology, the sequence data in a single project can reach Petabyte-scale or Terabyte-scale nucleotides. Counting demand for the abundance of these sequencing data is beyond the memory and computing capacity of single computing node, and how to process it efficiently is a challenge on a high-performance computing cluster. As such, we propose SWAPCounter, a highly scalable distributed approach for kmer counting. This approach is embedded with an MPI streaming I/O module for loading huge data set at high speed, and a counting bloom filter module for both memory and communication efficiency. By overlapping all the counting steps, SWAPCounter achieves high scalability with high parallel efficiency. The experimental results indicate that SWAPCounter has competitive performance with two other tools on shared memory environment, KMC2, and MSPKmerCounter. Moreover, SWAPCounter also shows the highest scalability under strong scaling experiments. In our experiment on Cetus supercomputer, SWAPCounter scales to 32,768 cores with 79% parallel efficiency (using 2048 cores as baseline) when processing 4 TB sequence data of 1000 Genomes. The source code of SWAPCounter is publicly available at https://github.com/mengjintao/SWAPCounter.

High-resolution global ocean general circulation models (OGCMs) play a key role in accurate ocean forecasting. However, the models of the operational forecasting systems are still not in high resolution due to the subsequent high demand for large computation, as well as the low parallel efficiency barrier. Good scalability is an important index of parallel efficiency and is still a challenge for OGCMs. We found that the communication cost in a barotropic solver, namely, the preconditioned conjugate gradient (PCG) method, is the key bottleneck for scalability due to the high frequency of the global reductions. In this work, we developed a new algorithm—a communication-avoiding Krylov subspace method with a PCG (CA-PCG)—to improve scalability and then applied it to the Nucleus for European Modelling of the Ocean (NEMO) as an example. For PCG, inner product operations with global communication were needed in every iteration, while for CA-PCG, inner product operations were only needed every eight iterations. Therefore, the global communication cost decreased from more than 94.5% of the total execution time with PCG to less than 63.4% with CA-PCG. As a result, the execution time of the barotropic modes decreased from more than 17,000 s with PCG to less than 6000 s with CA-PCG, and the total execution time decreased from more than 18,000 s with PCG to less than 6200 s with CA-PCG. Besides, the ratio of the speedup can also be increased from 3.7 to 4.6. In summary, the high process count scalability when using CA-PCG was effectively improved from that using the PCG method, providing a highly effective solution for accurate ocean simulation.

Statistical machine translation is often criticized for slow decoding time. We address this issue by presenting a new tool for enabling Moses, a state of the art machine translation system, to be run on gLite based Grid infrastructures. It implements a workflow model for equally distributing the decoding task among several worker nodes in a cluster. We report experimental results for possible speed-ups and envision how natural language processing scientists can benefit from existing Grid infrastructures for solving processing, storage and collaboration issues.

How the brain separates sounds

IntroductionOrthoptic exercises have been the primary treatment for convergence insufficiency since this condition's first description in 1855. It is presumed that exercises work by improving fusional convergence. In recent years, research from eye movement laboratories has challenged our theories on the nature and dynamics of convergence, the effect of convergence exercises, and the etiology of primary convergence insufficiency.MethodsA review of the ophthalmological, optometric, and basic science literature was done to retrieve the most recent research on vergence eye movements and convergence insufficiency.ResultsConvergence appears to be a bi-phasic response to a change in stimulus position in depth. The first phase, which may represent the contribution of proximal convergence, is not under visual feedback, is fast with a short latency, and is triggered by stimuli moving rapidly in depth or by large, sudden changes in fixation. This phase is followed by a slow vergence movement with a slightly longer latency, triggered by small disparity vergence errors. The second phase is under the control of visual feedback, and represents the contributions of fusional and accommodative convergence. Eye movement recordings indicate that the velocity and amplitude of the first phase of convergence are temporarily adaptable with exercises. The second phase does not appear to be amenable to training. Tonic convergence is also trainable.ConclusionConvergence exercises are effective in temporarily improving the dynamics of proximal and tonic convergence, but have little effect on fusional or accommodative convergence.

1 2 s c 1. Introduction sequential overhead; 2) adding cores often does not result in corresponding speedups: if we get a speedup of 3x with 5 cores, and a speedup of 6x with 10 cores, then the parallel efficiency is only 60%; 3) often the performance plateaus or even degrades after a certain number of cores due to insufficient parallel work, bottlenecks and communication costs. Good parallel scalability is obtained when the sequential overhead is low, the parallel efficiency is high, and bottlenecks and costs that limit the maximum number of cores can be avoided.

Achieving high scalability for dynamical adaptive algorithms in HPC is a non-trivial task. In this contex, explicit data migration is typically applied which comes with several challenges such as criteria when and where to migrate data or additional bandwidth requirements. In our work, we use an alternative to data-migration, namely compute-migration on cache-coherent memory systems. We focus on migrating computational power for simulations with dynamical adaptive grids with invasive paradigm. An extension to our existing core-distribution scheduler is presented, distributing the cores depending on the requirements specified by each parallel program instance. In addition, a programming pattern for the hybrid parallel application code is presented to overcome deadlock issues created by applying invasive computing. We validate our approach with benchmark computations for a simulation with artificial workload and furthermore for a realistic scenario based on dynamical adaptive shallow water simulations. Those benchmarks are conducted within a hybrid parallelization environment on a 40-core HPC node. On this shared-memory system, our invasive approach results in faster execution times and higher hardware utilization than the non-invasive approach. Our approach can be applied in general to similar classes of simulations on dynamical adaptive grids.

1. Introduction Ferroelectric-HfO2 (FE-HfO2) is a key technology enabler for energy-efficient memory devices because of its high scalability and CMOS-compatibility [1]. FE memory device is low-power, high-speed and high reliability by field-driven operation. FE memory device can be implemented in the form of capacitor, resistor, and transistor, which provides us design flexibility of memory system. Thanks to the material break-through and the device architecture innovation, FE memory device opens up new opportunities in memory market. In this talk, I will overview our recent research progress on FE-HfO2 memory devices and discuss future perspectives. 2. Capacitor memory - NVSRAM The most mature device structure is capacitor type. It is natural to replace conventional FE-material by scalable FE-HfO2. We can take an advantage of low power operation of FE-HfO2 for smart power management in IoT application. IoT sensor node devices are expected to operate in an intermittent mode. The active rate of a transistor is much lower than clock frequency in IoT device. In order to suppress standby leakage power, especially in SRAM, it is important to bring the transistors in sleep mode as much as possible. Normally-off computing is the idea that stores the current state data in NV memory, turns the power off, and restore the data after power-on without much latency and power overhead. NV-SRAM [2] has been revisited by using FE-HfO2 which realizes good scalability as well as cost effective process. NV-SRAM has been designed, fabricated by integrating FE-HfO2 capacitor [3] in back-end process as shown in Fig. 1. Store, power-off, and recall operation are successfully demonstrated. 3. Resistive memory - FTJ Ferroelectric Tunnel Junction (FTJ) memory is an emerging memory for high capacity memory. A ferroelectric thin film is sandwiched by two electrodes, which works as resistive change memory, as shown in Fig. 2. FTJ was proposed back in 1970s [4] and current state-of-the-art nanoscale ferroelectric thin film technologies are to finally realize it. FTJ utilizes polarization switching to change on-sate and off-state tunneling electroresistance (TER). Design guideline and high TER as much as >30 has been recently demonstrated by FE-HfO2 (Fig. 2) [5]. FTJ also shows multi-level cell operation and high resistance, which are useful for hardware AI application. Moreover, scalability has been thoroughly investigated by self-consistent potential and non-equilibrium Green function method to compete with other high capacity memories (Fig. 3) [6]. 4. Transistor memory - FeFET Ferroelectric FET (FeFET) memory is a transistor which has a thin FE layer as gate insulator. This is another type of device structure for high capacity memory. Recently, 3D stacked FeFET has been proposed [7], which can possibly compete with NAND flash memory in terms of memory capacity.There are several challenges to realize such 3D stacked FeFET using conventional poly-Si channel. Poly-Si channel has low mobility and forms a low-k interfacial layer which causes voltage loss and reliability degradation by charge trapping. In this work, we propose to use amorphous oxide semiconductor, IGZO [8], as an alternative channel material. IGZO channel provides high mobility as a deposited channel and prevent low-k interfacial layer formation. We have demonstrated ferro- electricity in the combination of FE-HfO2 and IGZO (Fig. 4), and large memory window with nearly ideal subthreshold swing and high endurance operations [9]. 5. Conclusions FE-HfO2 is a key technology enabler for energy-efficient computing because of its high scalability and CMOS-compatibility. NVSRAM serves for smart power management in IoT applications. FTJ and FeFET have a potential for low power and high capacity memory as well as machine learning accelerator. Acknowledgment The author acknowledges Nozomu Ueyama, Yusaku Tagawa, Fei Mo, Kiyoshi Takeuchi, Takuya Saraya and Toshiro Hiramoto for technical discussion and help. This work is partly supported by JST CREST 16815651, JST PRESTO 15656058, MEXT KAKENHI 16K18085 and 18H01489.

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> We propose a cross-layer design for resource-constrained systems that simultaneously decode multiple video streams on multiple parallel processors, cores, or processing elements. Our proposed design explicitly considers the coder specific application characteristics such as the decoding dependencies, decoding deadlines, and distortion impacts of different video packets (e.g., frames, slices, groups of slices etc.). The key to the cross-layer design is the resource management control plane (RMCP) that coordinates the scheduling and processor selection across the active applications. The RMCP deploys a priority-queuing model that can evaluate the system congestion and predict the total expected video quality for the set of active decoding tasks. Using this model, we develop a robust distortion- and delay-aware scheduling algorithm for video packets. This algorithm aims to maximize the sum of achieved video qualities over all of the decoded video sequences. Additionally, we propose a processor selection scheme intended to minimize the delays experienced by the queued video packets. In this way, the number of missed decoding deadlines is reduced and the overall decoded video quality is increased. We compare queuing-theoretic based scheduling strategies to media agnostic scheduling strategies (i.e., earliest-deadline-first scheduling) that do not jointly consider the decoding deadlines and distortion impacts. Our results illustrate that by directly considering the video application's properties in the design of a video decoding system, significant system performance gains on the order of 4 dB peak-signal-to-noise ratio can be achieved. </para>

Parallel-vector algorithms for particle simulations on shared-memory multiprocessors

Machine-learning potentials (MLPs) trained on data from quantum-mechanics based first-principles methods can approach the accuracy of the reference method at a fraction of the computational cost. To facilitate efficient MLP-based molecular dynamics and Monte Carlo simulations, an integration of the MLPs with sampling software is needed. Here, we develop two interfaces that link the atomic energy network (ænet) MLP package with the popular sampling packages TINKER and LAMMPS. The three packages, ænet, TINKER, and LAMMPS, are free and open-source software that enable, in combination, accurate simulations of large and complex systems with low computational cost that scales linearly with the number of atoms. Scaling tests show that the parallel efficiency of the ænet-TINKER interface is nearly optimal but is limited to shared-memory systems. The ænet-LAMMPS interface achieves excellent parallel efficiency on highly parallel distributed-memory systems and benefits from the highly optimized neighbor list implemented in LAMMPS. We demonstrate the utility of the two MLP interfaces for two relevant example applications: the investigation of diffusion phenomena in liquid water and the equilibration of nanostructured amorphous battery materials.

Parallel imaging is a robust method for accelerating the acquisition of magnetic resonance imaging (MRI) data, and has made possible many new applications of MR imaging. Parallel imaging works by acquiring a reduced amount of k-space data with an array of receiver coils. These undersampled data can be acquired more quickly, but the undersampling leads to aliased images. One of several parallel imaging algorithms can then be used to reconstruct artifact-free images from either the aliased images (SENSE-type reconstruction) or from the undersampled data (GRAPPA-type reconstruction). The advantages of parallel imaging in a clinical setting include faster image acquisition, which can be used, for instance, to shorten breath-hold times resulting in fewer motion-corrupted examinations. In this article the basic concepts behind parallel imaging are introduced. The relationship between undersampling and aliasing is discussed and two commonly used parallel imaging methods, SENSE and GRAPPA, are explained in detail. Examples of artifacts arising from parallel imaging are shown and ways to detect and mitigate these artifacts are described. Finally, several current applications of parallel imaging are presented and recent advancements and promising research in parallel imaging are briefly reviewed.

Multi-processor architectures have gained interest recently because of their ability to exploit programmable silicon parallelism at acceptable power-efficiency figures. Despite the potential benefit they offer over single-processor architectures, it is unresolved how one can write compact and efficient programs for multiple parallel cores. In this paper, we propose the use of a synchronous hardware description language to program a network of small PicoBlaze processors. The partitioning of a multiprocessor program over multiple cores is straightforward because the input specification is fully parallel. A systematic transformation process converts the parallel input specification into concurrent PicoBlaze programs. We demonstrate the mapping of a cryptographic design (AES) onto four PicoBlaze processors, showing almost linear speedup over an equivalent single-core design.