Graphene-based materials and their applications in electrolyte-gated transistors for sensing

This work develops the first frequency-dependent small-signal model for graphene electrolyte-gated field-effect transistors (EGFETs). Graphene EGFETs are microfabricated to measure intrinsic voltage gain, frequency response, and to develop a frequency-dependent small-signal model. The transfer function of the graphene EGFET small-signal model is found to contain a unique pole due to a resistive element, which stems from electrolyte gating. Intrinsic voltage gain, cutoff frequency, and transition frequency for the microfabricated graphene EGFETs are approximately 3.1 V/V, 1.9 kHz, and 6.9 kHz, respectively. This work marks a critical step in the development of high-speed chemical and biological sensors using graphene EGFETs.

In this work, an electrolyte-gated graphene field-effect transistor is developed for Gd3+ ion detection in water. The source and drain electrodes of the transistor are fabricated by photolithography on polyimide, while the graphene channel is obtained by inkjet-printing a graphene oxide ink subsequently electro-reduced to give reduced graphene oxide. The Gd3+-selective ligand DOTA is functionalized by an alkyne linker to be grafted by click chemistry on a gold electrode without losing its affinity for Gd3+. The synthesis route is fully described, and the ligand, the linker and the functionalized surface are characterized by electrochemical analysis and spectroscopy. The as functionalized electrode is used as gate in the graphene transistor so to modulate the source-drain current as a function of its potential, which is itself modulated by the concentration of Gd3+captured on the gate surface. The obtained sensor is able to quantify Gd3+ even in a sample containing several other potentially interfering ions such as Ni2+, Ca2+, Na+ and In3+. The quantification range is from 1 pM to 10 mM, with a sensitivity of 20 mV dec−1 expected for a trivalent ion. This paves the way for Gd3+ quantification in hospital or industrial wastewater.

Electrolyte-gated graphene field-effect transistors are here proposed for biosensing applications. To this end, a label-free immunosensor based on this technology is employed for the sensitive and selective detection of IgG. Differently from the typical approach based on the bioreceptor immobilization onto a graphene layer, in this work sensitivity in the lower femtomolar range can be reached thanks to the formation of a closely packed layer of anti-IgG receptors anchored to the gold gate electrode.

Chapter 3 - Field Effect Transistors: FETs and HEMTs

A comparative study on the edge states in phosphorene quantum dots and rings

Design and study of phosphorene nanoribbons as a perfect absorber and polarizer in mid-IR range

Transistors based on two-dimensional (2D) materials have been considered one of the most promising techniques after the silicon-based technique. However, unlike the diversity and popularity of the study on the channel materials for 2D transistors, the research on dielectric materials received insufficient attention in the past decade. So far, the main candidates used as dielectric materials for 2D transistors are limited to native oxides such as SiO2, deposited high-κ oxides such as HfO2 by atomic layer deposition (ALD), and van der Waals crystals such as hexagonal boron nitride (h-BN). However, these materials have their respective problems. The native oxides, SiO2 as the representative, have relatively low dielectric constant and are limited by their parent materials, which can hardly be used for other semiconductors. The mechanism of deposition requires nucleation on the surface of the semiconductors, where the dangling-bond-free high-quality surface of 2D materials does not favor the uniform growth and leads to low-quality film and interface. The van der Waals crystals like h-BN are restricted by their crystal size and the dielectric constants are relatively low. Therefore, new candidates and techniques that can possibly satisfy the ultimate standards for dielectric materials in 2D transistors, i.e., scalable ultrathin high-κ materials with high quality, are urgently needed. It was found that the native oxides of liquid metals, such as gallium oxide (Ga2O3) from liquid gallium, could be prepared as ultrathin free-standing materials for applications. These ultrathin free-standing oxides might have potentials properties that meet the requirements as dielectric materials in 2D transistors. In this thesis, the potential properties of the free-standing Ga2O3 and its integration for high-performance 2D transistors are demonstrated. First, the morphology and dielectric properties, such as dielectric constant, breakdown field, optical band gap, etc. are characterized. Ultrathin thickness of less than 3 nm and an ultra-flat surface are measured. A high dielectric constant about 30 and high breakdown field about 11 MV/cm are extracted. A low equivalent oxide thickness (EOT) about 0.4 nm is calculated. These properties therefore indicate the free-standing Ga2O3 as an ultrathin and uniform high-κ dielectric material, which meets the requirements for high-performance 2D transistors. A surface-tension-driven method of wafer-scale preparation is introduced, providing the scalability for device fabrication. Second, the free-standing Ga2O3 is integrated in 2D MoS2 field-effect transistors (FETs) as dielectric layer. Subthreshold swing down to 60 mV/dec is obtained, close to the thermal limit at room temperature. Low leakage current density about 4×10–7 A cm–2 and low density of interfacial state about 4×1011 eV–1 cm–2 are extracted. Immunity to the short-channel effect is revealed with short-channel FETs with channel lengths down to about 28 nm. Scalable device fabrication is demonstrated with FET arrays and logic gates, including NOT, NAND, NOR, AND, XOR. The high performance is attributed to the outstanding dielectric properties of the Ga2O3 and the van der Waals integration. Third, the passivation ability of the ultrathin Ga2O3 as an encapsulation layer is evaluated with black phosphorus (BP) and 1T' MoTe2, which are representatives of air-sensitive 2D materials. Dramatic increases in retention time of both optical and electrical properties are obtained, due to the self-limiting oxidation that forms dense native oxide against O2, H2O, etc. in an ambient environment. Owing to the facile selective etching of the ultrathin Ga2O3, direct device fabrication without removal of the encapsulation layer. Dual-gate FETs can be directly fabricated with encapsulated BP, using the Ga2O3 simultaneously as encapsulation and dielectric material. This dissertation, therefore, exhibits that the free-standing native oxide from liquid metal has desired properties as dielectric material and encapsulation for the fabrication of high-performance 2D transistors.

Field effect transistors: FETs and HEMTs

Among the plethora of soluble and easy processable organic semiconductors, 6,13-Bis(triisopropylsilylethynyl)pentacene (TIPS-P5) is one of the most promising materials for next-generation flexible electronics. However, based on the information reported in the literature, it is difficult to exploit in field-effect transistors the high-performance characteristics of this material. This article correlates the HMDS functionalization of the silicon substrate with the electrical characteristics of TIPS-P5-based bottom gate organic field-effect transistors (OFETs) and electrolyte-gated organic field-effect transistors (EGOFETs) fabricated over the same platform. TIPS-P5 transistors with a double-gate architecture were fabricated by simple drop-casting on Si/SiO2 substrates, and the substrates were either functionalized with hexamethyldisilazane (HMDS) or left untreated. The same devices were characterized both as standard bottom-gate transistors and as (top-gate) electrolyte-gated transistors, and the results with and without HMDS treatment were compared. It is shown that the functionalization of the silicon substrate negatively influences EGOFETs performance, while it is beneficial for bottom-gate OFETs. Different device architectures (e.g., bottom-gate vs. top-gate) require specific evaluation of the fabrication protocols starting from the effect of the HMDS functionalization to maximize the electrical characteristics of TIPS-P5-based devices.

The application of Field Effect Transistors (FETs) to sensors and biosensors allows a mass production, low cost, small size, fast response and, also, the possibility of integrating the device and conditioning signal circuit in the same integrated circuit (IC). The Ion Sensitive Field Effect Transistor (ISFET), invented in 1970 by Piet Bergveld (1), is a device similar to the conventional Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), except that the metal gate is replaced by an inert electrode/pseudo electrode and a sample solution, in order to expose the gate oxide layer to ions present in the solution. The solution charges change the electrical potential in the gate oxide surface and, consequently, the device threshold voltage changes as a function of the ion concentration in the sample solution, being used as a pH sensor. Thus, the ISFET is a very promising device to Point-of-Care (POC) monitoring, such as COVID-19 control (2) and for continuous in vivo monitoring ion activity in biological processes (3)-(6).The BESOI (Back Enhanced Silicon-On-Insulator) MOSFET is a device patented in 2015 by João Antonio Martino and Ricardo Cardoso Rangel (7). This device is easy to fabricate and low cost. In the last years, the research using this device as a sensor/biosensor has been done (8)-(14). This paper presents, for the first time, the BESOI MOSFET working as an Ion Sensitive Field Effect Transistor (ISFET): the BESOI ISFET. Therefore, the focus of this work is to study the device electrical behavior influenced for pH standard solutions.The BESOI ISFET was fabricated at Integrated System Laboratory (LSI) from University of Sao Paulo (USP), Brazil. It is a planar device made on a SOI (Silicon-On-Insulator) wafer with three conventional photolithography steps, in an analogous way to previous work (15) and one more photolithography step to create microchannel and microreservoirs with SU-8 (16) layer to contain the sample solution. The wafer has no doping process (there is only the natural wafer doping of 1015 cm-3). The silicon channel layer and the gate oxide (SiO2) thicknesses are 10 nm and 25 nm, respectively. The buried oxide layer thickness is 200 nm. The drain and source contacts are fabricated with nickel and the contact pads using aluminum. The Figure 1 presents the final device layout and the Figure 2 shows the device schematic drawn.Differently from a conventional ISFET, where the drain current flows at the front interface, in the BESOI ISFET the drain current flows at the back interface. As the BESOI ISFET is a non-intentionally doped device, the free conduction charge layer is formed by biasing the Back Gate electrode (VGB). When a positive enough VGB is applied, electrons are attracted and accumulated at the back interface, and therefore, current flows from source to drain when VDS (Drain bias) is applied. A Platinum (Pt) pseudo-electrode is used to apply front-gate voltage (VGF) to the sample solution.The experimental drain current (IDS) as a function of the front-gate voltage (VGF), for 25 V applied at the back-gate (VGB), is presented in Figure 3.A, which is possible to observe that the neutral pH (pH7) curve stayed between the acid pH (pH4) curve, in the left, and alkaline pH (pH10) curve, in the right. This result shows that the threshold voltage (VTH) is lower for acid pH and higher for alkaline pH, what is compatible with the conventional ISFET results present in the literature (17). To corroborate the experimental measurement result, the device simulation was made with TCAD-Sentaurus (18), based in the paper (19). Figure 3.B shows the same trend for the simulated device with pH solution for any VGB value.In Figure 4, the threshold voltage was analyzed as a function of the pH for different VGB values. The VTH increases (becomes more positive) for alkaline pH values, regardless of the VGB applied. However, the VTH variation in the pH range, between pH4 and pH10, is different for different VGB values. With higher VGB applied, higher is the VTH variation. In Figure 5 Is possible to see clearly that the sensitivity (ΔVTH /ΔpH) increases with the VGB increase probably due to the small influence of the series resistance. In another hand, the acquired sensitivity values for VGB higher than 15 V in this work (about 25-33 mV/pH, approximately), is compatible with results present in the literature for conventional ISFETs with silicon dioxide (SiO2) for gate insulator (20). Figure 1

Printed electronics (PE) is a fast-growing field with promising applications in wearables, smart sensors, and smart cards, since it provides mechanical flexibility, and low-cost, on-demand, and customizable fabrication. To secure the operation of these applications, true random number generators (TRNGs) are required to generate unpredictable bits for cryptographic functions and padding. However, since the additive fabrication process of the PE circuits results in high intrinsic variations due to the random dispersion of the printed inks on the substrate, constructing a printed TRNG is challenging. In this article, we exploit the additive customizable fabrication feature of inkjet printing to design a TRNG based on electrolyte-gated field-effect transistors (EGFETs). We also propose a printed resistor tuning flow for the TRNG circuit to mitigate the overall process variation of the TRNG so that the generated bits are mostly based on the random noise in the circuit, providing a true random behavior. The simulation results show that the overall process variation of the TRNGs is mitigated by 110 times, and the generated bitstream of the tuned TRNGs passes the National Institute of Standards and Technology - Statistical Test Suite. For the proof of concept, the proposed TRNG circuit was fabricated and tuned. The characterization results of the tuned TRNGs prove that the TRNGs generate random bitstreams at the supply voltage of down to 0.5 V. Hence, the proposed TRNG design is suitable to secure low-power applications in this domain.

The role of graphene patterning in field-effect transistor sensors to detect the tau protein for Alzheimer's disease: Simplifying the immobilization process and improving the performance of graphene-based immunosensors

Modeling of bias-induced changes of organic field-effect transistor characteristics

In the domain of printed electronics (PE), field-effect transistors (FETs) with an oxide semiconductor channel are very promising. In particular, the use of high gate-capacitance of the composite solid polymer electrolytes (CSPEs) as a gate-insulator ensures extremely low voltage requirements. Besides high gate capacitance, such CSPEs are proven to be easily printable, stable in air over wide temperature ranges, and possess high ion conductivity. These CSPEs can be sensitive to moisture, especially for high surface-to-volume ratio printed thin films. In this paper, we provide a comprehensive experimental study on the effect of humidity on CSPE-gated single transistors. At the circuit level, the performance of ring oscillators (ROs) has been compared for various humidity conditions. The experimental results of the electrolyte-gated FETs (EGFETs) demonstrate rather comparable currents between 30%-90% humidity levels. However, the shifted transistor parameters lead to a significant performance change of the RO frequency behavior. The study in this paper shows the need of an impermeable encapsulation for the CSPE-gated FETs to ensure identical performance at all humidity conditions.

Ge integrated on Si is a promising candidate for energy-efficient field effect transistor (FET) applications due to its high mobility and compatibility to CMOS technology. Nevertheless, using Ge in FET fabrication is challenging due to difficulties in controlling the transistor channel/gate oxide interface properties and suppressing crystal defects such as threading dislocations that arise from Ge integration on Si. Furthermore, the smaller bandgap of Ge compared to Si can give rise to higher band-to-band tunneling leakage currents [1-2]. All these challenges severely affect the on-state (Ion) and off-state (Ioff) currents. With respect to simulation, the majority of the physical models parameters are calibrated for Si. For Ge, the parameters are still less well known. In this work, we present the fabrication and characterization of vertical Ge-based p-channel Planar-Doped Barrier FETs (p-PDBFETs). Our experimental results are then used to calibrate our simulation model. Based on simulation data, an improved transistor design is proposed.