HammerFilter: Robust Protection and Low Hardware Overhead Method for RowHammer

In this paper, the dynamic random access memory (DRAM) cell technology is introduced and the important technological breakthroughs are reviewed. The criteria of DRAM memory cell design is discussed and the key fabrication technologies of 6F2 memory cell and stack capacitor DRAM cell are summarized. The technological evolution of array access transistor is also reviewed. The transistors with U-shaped transistor or FinFET and the fabrication process flow of 6F2 DRAM chip were discussed. Based upon the technical requirements for DRAM cell, the possible device technologies for the next generation DRAM cell was summarized. It is predicted that (1) U-shape channel transistor will be the mainstream technology for the future DRAM cell beyond 20 nm; (2) low k material will be required for decreasing the bitline parasitic capacitance; (3) sense-amplifier with better signal-noise margin will be required to ease the requirement of high aspect-ratio storage capacitance; (4) low power DRAM design will draw more attention, rather than increasing the storage capacity of DRAM.

In this work, a 1-transistor (1T) dynamic random access memory (DRAM) cell based on a tunnel field-effect transistor (TFET) is introduced and its operation physics demonstrated. It is structurally based on a pillar structure and surrounding gate, which gives a high scalability compared with the conventional 1T-1 capacitor (1C) DRAM cell so it can be easily made into a 4F2 cell array. The program operation is performed not by hole generation through impact ionization or gate-induced drain leakage but by hole injection from the source region unlike other 1T DRAM cells. In addition, the tunneling current mechanism of the device gives low power consumption DRAM operation and good retention characteristics to the proposed device.

The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure has the superior performance-higher retention time (RT) and weak temperature dependence. But the performance of TFET DRAM cell is sensitive to programming condition. In this paper, the guideline of programming optimization is discussed in detail by using simulation tool—Silvaco Atlas. Both the writing and reading operations of DG-TFET DRAM depend on the band-to-band tunneling (BTBT). During the writing operation, the holes coming from BTBT governed by Gate2 are stored in potential well under Gate2. A small negative voltage is applied at Gate2 to retain holes for a long time during holding “1”. The BTBT governed by Gate1 mainly influences the reading current. Using the optimized programming condition, the DG-TFET DRAM obtains the higher current ratio of reading “1” to reading “0” (107) and RT of more than 2 s. The higher RT reduces the refresh rate and dynamic power consumption of DRAM.

Dynamic random access memory (DRAM) is facing the challenge of technology scaling. The de-creasing feature size makes it harder to make DRAM cells which can keep the current data-holding time. When DRAM cells cannot hold data for a long time, DRAM chips need a more frequent refreshing operation. There-fore, in the near future, time and energy cost on DRAM refreshing will be no longer trivial. In this paper, we propose DRAM Error Correction Pointer (ECP), an error-correction-manner framework, to reduce DRAM re-freshes without data loss. We exploit the non-uniform feature of DRAM cells with respect to the data retention time. Compared with the conventional refreshing mechanisms, which refresh DRAM chips by the retention time of the leakiest cells, we refresh the chips much fewer times, and treat the not-in-time refreshed cells as fault elements. We use the structure of ECP as a fault tolerant element. By recording the data which are supposed to be written into the leaky cells in our DRAM-ECP structures, DRAM-ECP can significantly decrease refreshing frequency. When these data are to be read out, DRAM-ECP retrieves the data stored in ECPs and covers them to the corresponding position in the data row. Our experiments show that DRAM-ECP can reduce over 70% refreshing operations than the current refreshing mechanism and also get significant energy saving.

A process technology for 0.16 μm embedded dynamic random access memory (DRAM) with gate length of 0.16 μm both in nmos and pmos, respectively, and DRAM cell size of 0.28 μm2 is described. A major characteristic of this process is the integration of proven logic and DRAM cell process from stand-alone logic and DRAM device with minimum additional process steps, and thus enhance yield and reliability of fabricated device. The major features are dual gate oxides, triple gate electrodes, cobalt (Co) salicide in gate and junction except DRAM cell region, tungsten (W) interconnection for bit line and local interconnection, cylinder-type stack capacitor with NO insulator film, and multilayer metallization up to 5 metals. Saturation currents of nmos and pmos are 550 and 235 μA/μm, respectively, at 1.5 V operation. Newly developed process, so-called logic open etch module, which planarizes DRAM cell region before formation of active junction and salicidation, gives stable pmos operation and Co salicide resistance, and also makes void-free gap fill between adjacent word lines in DRAM cell. Low temperature oxidation at 700°C in NO film which is used as dielectric film in stack capacitor is developed, and thus prevent degradation both in pmos transistor and Co salicide. © 2004 The Electrochemical Society. All rights reserved.

Low power has become an important factor in the design of Very Large Scale Integration (VLSI) circuits such as memory elements and digital systems. This paper reviews the power savings in a Dynamic Random Access Memory (DRAM) cell which is designed by using FinFET (Fin Field Effect Transistor). Applying this technique in the architecture of DRAM Cell, a reduction in overall power consumption has been approximately obtained. The proposed circuit has advantages in ultra-low power VLSI design. The circuit has been designed and implemented in H-spice at 32nm Technology.

This study quantifies refresh degradation in 4F 2 vertical channel dynamic random-access memory (DRAM) cells using technology computer-aided design. The vertical architecture forms a floating body due to the absence of a body contact, where gate-induced drain leakage (GIDL) during hold leads to hole accumulation, channel potential elevation, and accelerated storage node voltage (SNV) loss. A buried channel array transistor reference with a body contact maintains stable retention up to 1000 ms by effectively discharging generated holes. In contrast, the vertical DRAM exhibits rapid SNV decay, failing at 19 ms. While drain-side doping underlap can suppress GIDL and improve retention, it significantly degrades on-current. To overcome this trade-off, a modified structure with a shortened back-gate underlap is proposed, achieving retention improvement from 80 ms to 160 ms while preserving drive current. These results provide design guidelines for reliable high-density DRAM cells.

We review our capacitor technology using (Ba,Sr)TiO3(BST) as a capacitor dielectric for dynamic random access memory (DRAM) application. Among a number of issues for BST capacitor process integration in DRAM cells, two important technologies are discussed. As an electrode technology, we proposeAllPErovskiteCapacitor (APEC) technology, in which conducting perovskite oxide of SrRuO3(SRO) is used as capacitor electrodes. For chemical vapor deposition (CVD) of BST, we propose In-situ Multi-Step (IMS) process, which is a sequential repetition of low temperature deposition of ultra thin BST film and crystallization in the same chamber. By using APEC technology and IMS CVD process of BST, we can simultaneously achieve good electrical characteristics (low leakage current and high permittivity) and good step coverage. The combination of APEC technology and IMS CVD process of BST is a promising BST capacitor process technology for future DRAMs.

Reversible logic is an emerging nanotechnology used in the design and implementation of nanotechnology and quantum computing with the main goal of reducing physical entropy gain. Significant work have been produced in the design of fundamental reversible logic structures and arithmetic units, and recent developments in sequential design of reversible circuits has opened new avenues in the implementation of reversible combinational circuits, such as the design and implementation of static (SRAM) and dynamic random-access memory (DRAM). In this paper, a novel 4*4 MLMR gate is presented which is used for controlling the read/write logic of a SRAM cell. Next, a reversible SRAM cell is designed and verified. Then, a novel 4*4 Reversible Decoder (RD) gate, implemented as a 2-to-4 decoder with low delay and cost is presented and verified, and its implementation shown in the construction of a 4×2 reversible SRAM array. Next, a dual-port SRAM cell is presented and verified, and its implementation in a synchronous n-bit reversible dual-port SRAM array is shown. Then, a reversible DRAM cell is presented and verified. The control logic for writing to the DRAM based on Peres gates is shown. The control logic and the DRAM cell are then implemented in a reversible 4×4 DRAM array.

One-transistor (1T) dynamic random-access memory (DRAM) has been widely studied for higher array density and obtaining three-dimensional (3-D) array stack viability by truncating the capacitor. However, its rather short retention time has been pointed out as a weak point compared with that of conventional one-transistor one-capacitor (1T1C) DRAM cell. The three dominating factors in determining the data retention in 1T DRAM can be sorted as diffusion, drift, and recombination, by which the programmed carriers are annihilated. In this study, out of those three major factors, the most predominant one is sought in the analytical and mathematical manners. It has been found that carrier diffusion has the key to modulation of the retention time of 1T DRAM and the other two factors are insignificantly small compared with diffusion. Error functions depending on both position and time were adopted to describe the distribution of programmed holes experiencing diffusion and drift in conjunction with solving the continuity equation. It has been concluded that carrier diffusion is the most dominant factor in determining the data retention in 1T DRAM, which suggests that proper ways of decelerating the carrier diffusion out of the channel be sought in optimally designing 1T DRAM cells.

In this paper, we proposed a novel 1T0C dynamic random-access memory (DRAM) cell with amorphous indium gallium zinc oxide (IGZO) channel. The gate-channel interface traps, which capture and emit carriers under bias stimulus, are the primary functional mechanism to enable this capacitor-less DRAM cell. TCAD simulation was carried out to simulate and investigate the memory effect of the interface traps. By optimizing electron capture cross section and the write voltage, the proposed IGZO DRAM 1T0C cell achieves a high retention time of 200s.

This paper explores the retention time (RT) properties of dynamic random-access memory (DRAM) arrays at cryogenic temperatures (4 K). We provide an in-depth examination of leakage sources to elucidate RT behaviour across different temperatures, and we conduct a study on the mismatch between DRAM cells, highlighting various trade-offs, including cell area, mismatch, retention time, and power consumption. Our findings offer valuable insights for circuit designers working on large-scale quantum computing or superconducting nanowire single-photon detectors (SNSPDs) arrays, especially those aiming to store data at 4 K to avoid the wiring bottleneck associated with outputting each pixel from 4 K to room temperature for data analysis.

We propose a novel SiGe superlattice band-gap engineered (SBE) capacitorless dynamic random access memory (DRAM) cell with the 30 nm channel by the 2D TCAD simulation. The SBE capacitorless DRAM cell used a common source structure and different metal layers for the top gate word line from the bottom gate word line to realize the 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (0.0036 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) feature size. From the 2D TCAD simulation of the SBE capacitorless DRAM cell, thanks to both the Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.8</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.2</sub> quantum well and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> physical energy barrier, we obtained the sensing margin of 6.4 μA and the retention time of 15 msec.

An array of substrate-plate trench-capacitor dynamic random access memory (DRAM) cells is used for quantification of parasitic leakage mechanisms, silicon defects, and device parametrics. Parasitic devices aid process characterization, parametric cross-correlations, and technology/device design-point evaluation. Used in conjunction with a functional monitor, the trench leakage monitor, is found to be a valuable semiconductor process-development vehicle to achieve functionality and cell-retention yield for a 4-Mb DRAM CMOS technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Dynamic random access memory (DRAM) is used as the main memory in every personal computer, due to its high density, high speed and efficient memory function. The ever-shrinking dimensions of DRAM cells with increasing packing density made the cell's capacitor size to be smaller. For successful operation of DRAM, a large cell capacitance (~ 25 fF) and low leakage current (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> or 1 fA/cell) are required. In a traditional Si-based capacitor, the target cell capacitance has been achieved by increasing the surface area of the capacitor. More recently, innovations have been made by development of the component materials. A metal electrode, TiN or Ru, and a dielectric material with a moderate-k value (k is the relative dielectric constant), such as HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (k ~ 25) and ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (k ~ 40), are being explored in giga-bit scale DRAMs. The minimum achievable t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> is ~ 0.7 nm for ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> which is being used currently in DRAM industry. However, the technology road map for memory devices states that t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> of less than 0.45 nm is necessary for the DRAMs with a design rule of <; 20 nm. Perovskite-based dielectric films such as SrTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> (STO) and (Ba, Sr)TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> were reported to exhibit k values of several hundreds. However, growth of these films showed very slow growth rate and much more complicated processes than growth of binary oxide with the atomic layer deposition (ALD) technique which is a method of choice for the growth of the dielectric films and electrodes in microelectronic devices. Therefore, material and process innovations are necessary for next generation DRAM capacitors.