Hardware-based Cryptographic Accelerator for Post Quantum Era

The development of near-term quantum computers, referred to as Noisy Intermediate-Scale Quantum (NISQ) computers, has progressed rapidly in the past few years resulting in several quantum computers which vary in their underlying technology and physical constraints. The performance of these computers also varies from one quantum algorithm to another. To enable efficient selection of the quantum computer that provides the highest output fidelity for a given application, an accurate noise modeling of each quantum hardware is required. However, noise modeling for a given application is a complex problem because of the unknown interaction between the quantum circuit parameters and the noise parameters of NISQ devices. We propose the use of Machine Learning (ML) to model the performance of different quantum computers at the application level. The ML models predict the output fidelity of the quantum application executed on different quantum computers given their publicly available physical constraints. We use a diverse training dataset to cover the key features for application-level benchmarking of the quantum hardware. Our results obtained from different superconducting quantum devices show that our proposed ML models enable cost-effective quantum computer selection for different quantum applications with different fidelity metrics.

Quantum computers are growing at a rapid pace. Trends show that the current decade could be the one in which quantum computers deliver commercial value. Today's quantum computers are overwhelmed by errors. To unlock their massive potential, a significant reduction in errors is required. Several qubit technologies are under research, e.g. superconducting, neutral atoms, trapped ions, photons and silicon. For useful quantum computing on these qubit technologies, Quantum Error Correction (QEC) turns unreliable physical qubits into useful logical qubits. QEC requires solving a real-time, large data volume decoding problem that determines the effect of physical noise on the computation carried out on logical qubits. The nature of the decoding problem depends on the qubit technology, choice of QEC code and mode of quantum computation. These are actively researched subjects in the quantum computing world. Hardware-based decoders that use Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuits (ASIC) technologies are the most promising solutions in terms of speed and scalability. However, the design methodology for these solutions typically suffers from long lead times and a lack of flexibility. We propose GridGenQ, a hardware design utility that automates part of the FPGA/ASIC design methodology for distributed QEC decoders. We show that with our novel solution, development time for such distributed hardware decoders can be reduced from several weeks to few minutes. This allows for fast prototyping of distributed decoder architectures to meet the requirements posed by a dynamic QEC landscape.

This thesis work presents the implementation and validation of image processing problems in hardware to estimate the performance and precision gain. It compares the implementation for the addressed problem on a Field Programmable Gate Array (FPGA) with a software implementation for a General Purpose Processor (GPP) architecture. For both solutions the implementation costs for their development is an important aspect in the validation. The analysis of the flexibility and extendability that can be achieved by a modular implementation for the FPGA design was another major aspect. This work is based upon approaches from previous work, which included the detection of Binary Large OBjects (BLOBs) in static images and continuous video streams [13, 15]. One addressed problem of this work is the tracking of the detected BLOBs in continuous image material. This has been implemented for the FPGA platform and the GPP architecture. Both approaches have been compared with respect to performance and precision. This research project is motivated by the MI6 project of the Computer Vision research group, which is located at the Bonn-Rhein-Sieg University of Applied Sciences. The intent of the MI6 project is the tracking of a user in an immersive environment. The proposed solution is to attach a light emitting device to the user for tracking the created light dots on the projection surface of the immersive environment. Having the center points of those light dots would allow the estimation of the user’s position and orientation. One major issue that makes Computer Vision problems computationally expensive is the high amount of data that has to be processed in real-time. Therefore, one major target for the implementation was to get a processing speed of more than 30 frames per second. This would allow the system to realize feedback to the user in a response time which is faster than the human visual perception. One problem that comes with the idea of using a light emitting device to represent the user, is the precision error. Dependent on the resolution of the tracked projection surface of the immersive environment, a pixel might have a size in cm2. Having a precision error of only a few pixels, might lead to an offset in the estimated user’s position of several cm. In this research work the development and validation of a detection and tracking system for BLOBs on a Cyclone II FPGA from Altera has been realized. The system supports different input devices for the image acquisition and can perform detection and tracking for five to eight BLOBs. A further extension of the design has been evaluated and is possible with some constraints. Additional modules for compressing the image data based on run-length encoding and sub-pixel precision for the computed BLOB center-points have been designed. For the comparison of the FPGA approach for BLOB tracking a similar implementation in software using a multi-threaded approach has been realized. The system can transmit the detection or tracking results on two available communication interfaces, USB and RS232. The analysis of the hardware solution showed a similar precision for the BLOB detection and tracking as the software approach. One problem is the strong increase of the allocated resources when extending the system to process more BLOBs. With one of the applied target platforms, the DE2-70 board from Altera, the BLOB detection could be extended to process up to thirty BLOBs. The implementation of the tracking approach in hardware required much more effort than the software solution. The design of high level problems in hardware for this case are more expensive than the software implementation. The search and match steps in the tracking approach could be realized more efficiently and reliably in software. The additional pre-processing modules for sub-pixel precision and run-length-encoding helped to increase the system’s performance and precision.

Field Programmable Gate Arrays (FPGAs) play a significant role in computationally intensive network processing due to their flexibility and efficiency. Particularly with the high-level abstraction of the P4 network programming model, FPGA shows a powerful potential for packet processing. By supporting the P4 language with FPGA processing, network researchers can create customized FPGA-based network functions and execute network tasks on accelerators directly connected to the network. A feature of the P4 language is that it is stateless; however, the FPGA implementation in this research requires state information. This is accomplished using P4 externs to describe the stateful portions of the design and to implement them on the FPGA using High-Level Synthesis (HLS). This paper demonstrates using an FPGA-based SmartNIC to efficiently extract source-destination IP address information from network packets and construct anonymized network traffic matrices for further analysis. The implementation is the first example of the combination of using P4 and HLS in developing network functions on the latest AMD FPGAs. Our design achieves a processing rate of approximately 95 Gbps with the combined use of P4 and High-level Synthesis and is able to keep up with 100 Gbps traffic received directly from the network.

Quantum error correction (QEC) is required in quantum computers to mitigate the impact of errorson physical qubits. The goal is to optimize the neural network for high decoding performance whilemaintaining a minimalistic hardware implementation. The errors associated with decoherence can bereduced by adopting QEC schemes that encode multiple imperfect physical qubits into a logical quantumstate, similar to classical error correction. The relevance of these studies lies in the mathematicaland software modeling and implementation of corrective codes to correct several types of quantumerrors in the development and implementation of quantum algorithms for solving classes of problems ofa classical nature. The scientific novelty of this direction is expressed in the elimination of one of theshortcomings of the quantum computing process. The development of the theory and principles for constructingmodeling systems that are resistant to external interference (dependence of data distortion onnoise, dependence of the error of a quantum computing process on the measure and purity of entanglement)for modeling quantum computing is a dynamic area, as evidenced by a large number of existingmodels reflecting certain quantum computational processes and phenomena (quantum teleportation,parallelism, entanglement of quantum states) and scientific papers. Although quantum computing is notyet ready to move from theory to practice, it is nevertheless possible to reasonably guess what form aquantum computer might take, or, more importantly for programming language design, what interface itwould be possible to interact with such a quantum computer. It is natural to apply the lessons learnedfrom the programming of classical computing to quantum computing. The analysis of works in this areashowed that a new qualitative level has now been reached, which opens up promising opportunities forthe implementation of multi-qubit quantum computing. Prospects for implementation and developmentare associated not only with technological capabilities, but also with the solution of issues of buildingeffective quantum systems for solving actual mathematical problems, cryptography problems and control(optimization) problems.

The present work investigates Multi – channel Active Vibration Control (AVC) of a composite research wing model and shell structure using modified Filtered × Least Mean Square (F×LMS) algorithm on Field Programmable Gate Arrays (FPGAs). AVC, using Digital Signal Processing (DSP) techniques are cost effective. But FPGAs, consuming small silicon area, have emerged as a dominant technology in embedded applications with potential features like high speed processing and low power consumption. Prominent features like high-speed parallel processing architecture along with hardware reconfigurability facilitates its usage to be wide spread in signal processing applications. An adaptive active vibration control system based on feed forward modified F×LMS algorithm implemented on FPGA hardware is presented here. The results from the Multi channel real time AV C studies are brought out in the paper.

The combination of hardware acceleration and flexibility make FPGAs (field programmable gate arrays) important to image processing applications. There is also a need for efficient, flexible hardware/software codesign environments that can balance the benefits and costs of using FPGAs. Image processing applications often consist of pipeline of components where each component applies a different processing algorithm. Components can be implemented for FPGAs or software. Such systems enable an image analyst to work with either FPGA or software implementations of image processing algorithms for a given problem. The pipeline assignment problem chooses from alternative implementations of pipeline components to yield the fastest pipeline. Our codesign system solves the pipeline assignment problem to provide the most effective implementation automatically, so the image analyst can focus solely on choosing components, which make up the pipeline. However, the pipeline assignment problem is NP complete. An efficient, dynamic solution to the pipeline assignment problem is a desirable enabler of codesign systems which use both FPGA and software implementations. This paper is concerned with solving pipeline assignment in this context. Consequently, we focus on optimal and heuristic methods for fast (fixed time limit) runtime pipeline assignment are investigated. We present experimental finding for pipelines of twenty or fewer components, which show that in our environment, optimal runtime solutions are possible for smaller pipelines and nearly optimal heuristic solutions are possible for larger pipelines.

In the field of microlithography, conventional computers are widely used for mask optimization. Recent progress of quantum and quantum-inspired computers has encouraged the development of quantum algorithms for numerous applications. So far, no method has been established for solving mask optimization problems with quantum computers. We introduced a simple model that describes the mask optimization problem as a quadratic unconstrained binary optimization (QUBO) problem, which is easily implemented on these computers. For simplicity, we assume there exists a target image profile on the wafer. The target can be the image of an existing mask or a virtual ideal mask which may be designed as a pixelated mask having a continuous transmission distribution. The solution is evaluated as the difference between the simulated image profile on the wafer surface and the target profile.

Neural networks (NNs) are used in numerous applications such as audio–video processing and image classification. NNs can address the limitations of the traditional computer algorithms. Recently, the research utilizing field-programmable gate arrays (FPGAs) to implement NNs is on the rise due to low power dissipation, easy and fast reconfigurability offered by these platforms. This is due to the research and development efforts put into the design optimization to improve the throughput of FPGAs. The integration of appropriate hardware with advanced artificial intelligence (AI) software presents many challenges. This paper offers a generalized model of NNs on a FPGA device. In addition, it presents the design process for the high-level synthesis (HLS) tools to implement the project on FPGA. This paper shows the results of latency, timing, pre- and post-synthesis, implementation, and hardware utilization on Xilinx FPGA target device. In this paper, NN for XOR logic gate operation is performed and verified by using HLS tool, and FPGA implementation is proposed. The NN and backpropagation algorithm are developed in high-level programming languages like Python, Java, C, C++. The training part of the NN has been done by using open-source software Dev C++, and tuned weights are taken to Xilinx Vitis HLS. Simulation, synthesis, and implementation are performed by using Xilinx Vitis HLS and Vivado 2020.1 electronic design automation (EDA) tools. NN architecture with tuned weights is implemented on Xilinx ZYNQ FPGA target device. This paper shows that we were able to achieve latency in one clock cycle interval through pipeline and array partition.KeywordsHigh-level synthesis (HLS)Neural networks (NNs)Register transfer level (RTL)Field-programmable gate arrays (FPGAs)Systems on chip (SOC)Artificial intelligence (AI)Graphic processing units (GPUs)Generalized NNs (GNN)Recurrent neural network (RNN)Feed-forward neural networks (FFNNs)

In the image and video processing field of mobile devices, edge detection is a fundamental technique for image segmentation, feature extraction and object tracking. Due to its high computational time in software implementation, we need to find a more efficient hardware approach to improve edge detection performance. With the development of Field Programmable Gate Array (FPGA) technology, the real-time parallel processing of huge video data stream using FPGA can be implemented because of FPGA reconfigurable and dedicated structure. In this paper, we present a FPGA-based implementation of edge detection technique for real-time pattern recognition applications and parallel processing. We propose a unique structure of Sobel Edge Detection on FPGA, which can significantly reduce the processing delay and improve the processing performance. The design is proved to be effective for real-time edge detection.

Information security in the post quantum era for 5G and beyond networks: Threats to existing cryptography, and post-quantum cryptography

This paper describes an algorithmic trading engine based on reconfigurable hardware, derived from a software implementation. Our approach exploits parallelism and reconfigurability of field-programmable gate array (FPGA) technology. FPGAs offer many benefits over software solutions, including a reduction in latency, while increasing overall throughput and computational density. All of which are important attributes to a successful algorithmic trading engine. Experiments show that the peak performance of our hardware architecture for algorithmic trading is 133 times faster than the corresponding software implementation. Six implementations can operate simultaneously on a Xilinx Vertex 5 xc5vlx30 FPGA on average, maximising performance and available resource usage.

When single Field-Programmable Gate Array(FPGA) deals with the huge amounts of data in high-speed network,low efficiency problem occurs.According to dual priority schedule algorithm for multi-processor and high-speed data acquisition and processing model based on multi-FPGA,a dual priority dynamic scheduling algorithm was proposed based on multi-FPGA.For strong real-time periodic tasks set in low priority queue,the Earliest Deadline Critical Laxity(EDCL) scheduling algorithm was given to determine the priority of task according to the degree of relaxation of the tasks.If the task was not finished when the promotion time was up,it would be promoted to high priority queue.For soft real-time periodic tasks,an algorithm was put forward to assign the tasks to middle priority queue and schedule them by delaying the deadline of tasks to dynamic blur threshold.The experimental results show that the proposed algorithms can well schedule strong real-time periodic tasks and guarantee the priority execution of important tasks,and it can also reduce miss rate of soft real-time periodic tasks caused by preemption.

This paper proposes a hardware oriented dropout algorithm for an efficient field-programmable gate array (FPGA) implementation. Dropout is a regularization technique, which is commonly used in neural networks such as multilayer perceptrons (MLPs), convolutional neural networks (CNNs), among others. To generate a dropout mask to randomly drop neurons during training phase, random number generators (RNGs) are usually used in software implementations. However, RNGs consume considerable FPGA resources in hardware implementations. The proposed method is able to minimize the resources required for FPGA implementation of dropout by performing a simple rotation operation to a predefined dropout mask. We apply the proposed method to MLPs and CNNs and evaluate them on MNIST and CIFAR-10 classification. In addition, we employ the proposed method in GoogLeNet training using own dataset to develop a vision system for home service robots. The experimental results demonstrate that the proposed method achieves the same regularized effect as the ordinary dropout algorithm. Logic synthesis results show that the proposed method significantly reduces the consumption of FPGA resources in comparison to the ordinary RNG-based approaches.

Chapter 14 - Embedded Processing Cores