Hardware design and description languages in IBM

UDL/I is a hardware design language for ASIC design developed in a Japanese LSI design language standardization project. A formal semantics of UDL/I is presented. There is no established way to define semantics of hardware design languages, because there is no general computation model for them. A definition method of formal semantics for UDL/I and semantics suitable for a standard language are developed. The basic idea is that the semantics of the language should be defined independently of simulators. The language provides an abstract model of hardware. The role of the language designer is to provide an abstract model of hardware which is natural and general for hardware designers and CAD engineers. The authors introduce a novel behavior model of hardware and define the semantics with a nondeterministic feature. >

The SHA-1 algorithm in Hash Function was widely used in TPM hardware design. This paper proposes a design of SHA-1 hash function operations on FPGA hardware implementations. Optimized the structure of the module about the algorithm, which implement the simulation and synthesis. The frequency and resource used was satisfied with the TPM specification. Implement the modules use Hardware Design Language in RTL level, could generate in Soft-Core, which used in Trusted Computing hardware design.

This paper presents an efficient approach for the implementation of typical DSP structures studied in class or conceived during research. This scheme is beneficial where the objective is to implement the physical working of complex DSP structures or algorithms without requiring detailed knowledge of hardware design and hardware description languages. The approach is based on the Xilinx System Generator for DSP tool, which integrates itself with the MATLAB based Simulink Graphics environment and relieves the user of the textual HDL programming. In addition to introducing this scheme for teaching of DSP, some useful examples based on Delta Sigma Modulators are also presented. These modulators are selected because they are an integral part of modern Analog to Digital Converters and encompass many important Signal Processing concepts. The advantage of this approach in DSP research in terms of reducing concept-to-Silicon design time and effort is also highlighted.

A process algebraic foundation has been developed for formal analysis of synchronous hardware designs represented through the commercially available hardware design language, ELLA. An underlying semantic foundation, based on input/output trace sets, is presented first through the use of state machines. Such a representation enables direct application of standard, fully automated trace equivalence checking tools. However, to overcome the computational limitations imposed by such analysis methods, the input/ output trace semantics is represented through a synchronous process algebra, EPA. Primitive processes in EPA denote the behaviour of primitive hardware components, such as delays or multiplexers, with composition operators corresponding to the different ways in which behaviours may be built. Of particular significance is the parallel composition operator which captures the machinery for building networks from other components/networks. Actions in EPA are structured and signify the state of input and output signals. This structure, however, is abstracted by developing an algebra for the actions. In particular, parallel composition on processes neatly lifts to a special (synchronous) product operation on actions. The EPA representation forms a good basis for semi-automated high-level symbolic manipulation and reasoning tools. First, the original design structure can be maintained, thus easing the problems of user level feedback from tools. Secondly, the application of EPA to ELLA enables a deterministic finite automation form for EPA terms. This provides a route to tractable symbolic verification and simulation, using a state evolution method to establish strong bisimulation properties. The method has been successfully applied to classes of unbounded state space systems.

We propose a new approach to define a formal semantics of a hardware design language (HDL) in Japanese LSI design language standardization project. Our approach is to separate the definition of semantics from simulators. Since the semantics includes nondeterminism, we can describe vagueness of circuit behavior such as dispersion of delays without linguistic ambiguity. We introduce a new computation model of hardware behaviour called NES (Nondeterministic Event Sequence) model. NES model is a very simple model of the computation in digital systems and provides an intuitive understanding of concurrent behaviour of HDL description without loss of mathematical strictness.

MDSL, which stands for Microcomputer Design and Simulation Language, is one of an ever growing number of computer hardware design (or description) languages or CHDL's. The introduction of any new language, particularly a new CHDL, is accompanied by a number of WHYs. Why should anyone bother to develop a CHDL? Why did we bother to develop a new one? Why did MDSL take the form it did?

Enabling new applications for mobile devices often requires the use of specialized hardware to reduce power consumption. Because of time-to-market pressure, current design methodologies for embedded applications require an early partitioning of the design, allowing the hardware and software to be developed simultaneously, each adhering to a rigid interface contract. This approach is problematic for two reasons: (1) a detailed hardware-software interface is difficult to specify until one is deep into the design process, and (2) it prevents the later migration of functionality across the interface motivated by efficiency concerns or the addition of features. We address this problem using the Bluespec Codesign Language~(BCL) which permits the designer to specify the hardware-software partition in the source code, allowing the compiler to synthesize efficient software and hardware along with transactors for communication between the partitions. The movement of functionality across the hardware-software boundary is accomplished by simply specifying a new partitioning, and since the compiler automatically generates the desired interface specifications, it eliminates yet another error-prone design task. In this paper we present BCL, an extension of a commercially available hardware design language (Bluespec SystemVerilog), a new software compiling scheme, and preliminary results generated using our compiler for various hardware-software decompositions of an Ogg Vorbis audio decoder, and a ray-tracing application.

Chapter 8 - Simulation, timing, and race conditions

This paper describes the development of using design automation tools at the Department of Electrical Engineering, University of Wisconsin-Platteville. A realistic design environment has been created. Students use the extensive facilities in this laboratory to undertake the design and integration of digital systems. Starting with the "Logic and Digital Design", in four digital courses, students use schematic capture tools (Orcad, Maxplus II, WorkView), hardware design language (AHDL, VHDL), implement EPLD, FPGA digital devices (Altera, Xilinx). This paper describes the environment in which the laboratory operates, the continuously support received from tool design and chip manufacturing companies, the available equipment and the accomplishments of the student projects during the two academic years from September 1994 to May 1996.

For decades, the streaming architecture of FPGAs has delivered accelerated performance across many application domains, such as option pricing solvers in finance, computational fluid dynamics in oil and gas, and packet processing in network routers and firewalls. However, this performance has come at the significant expense of programmability, i.e., the performance-programmability gap. In particular, FPGA developers use a hardware design language (HDL) to implement the application data path and to design hardware modules for computation pipelines, memory management, synchronization, and communication. This process requires extensive low-level knowledge of the target FPGA architecture and consumes significant development time and effort. To address this lack of programmability of FPGAs, OpenCL provides an easy-to-use and portable programming model for CPUs, GPUs, APUs, and now, FPGAs. However, this significantly improved programmability can come at the expense of performance, that is, there still remains a performance-programmability gap. To improve the performance of OpenCL kernels on FPGAs, and thus, bridge the performance-programmability gap, we apply and evaluate the effect of various optimization techniques on GEM, an N-body method from the OpenDwarfs benchmark suite.

hardware design language

Programming FPGAs has been an arduous task that requires extensive knowledge of hardware design languages (HDLs), such as Verilog or VHDL, and low-level hardware details. With OpenCL support for FPGAs, the design, prototyping and implementation of an FPGA is increasingly moving towards a much higher level of abstraction, when compared to the intrinsically low-level nature of HDLs. On the other hand, in the context of traditional (i.e., CPU) software development, OpenCL is still considered to be low-level and complex because the programmer needs to manually expose parallelism in the code. In this work, we present our approach to enhancing FPGA programmability via GLAF, a visual programming framework, to automatically generate synthesizable OpenCL code with an array of FPGA-specific optimizations. We find that our tool facilitates the development process and produces functionally correct and well-performing code on the FPGA for our molecular modeling, gene sequence search, and filtering algorithms.

In March 1980, the US Department of Defense (DoD) launched the Very High Speed Integrated Circuits program to advance the state of the art in highspeed integrated circuit technology, specifically for defense systems. In 1981 the Institute for Defense Analyses (IDA) arranged a workshop to define the requirements for such a standard. The DoD used the final report of the IDA workshop as a basis for defining a set of language requirements for the VHSIC Hardware Description Language (VHDL), issuing a request for proposal for a two-phase procurement of VHDL and its support environment. VHDL supports the design, documentation, and efficient simulation of hardware from the digital system level to the gate level. While designed to be independent of any underlying technology, design methodology, or environment tool, the language is also extendable toward various hardware technologies, design methodologies, and the varying information needs of design automation tools. The authors begin their discussion of VHDL by describing the concept of design entity, the language's primary abstraction mechanism. They then present a time-based execution model and describe VHDL's features, using a coded four-bit adder to illustrate the use of the most significant ones. Various figures are presented that contain the block diagrams and the code for this example.

Hardware/software security co-verification and vulnerability detection: An information flow perspective

Fundamental principles of modeling timing in hardware description languages