Hardware Implementation of a Fixed-Point Decoder for Low-Density Lattice Codes

This paper uses the reconstruction-computation-quantization (RCQ)paradigm to decode low-density parity-check (LDPC) codes. RCQ facilitates dynamic non-uniform quantization to achieve good frame error rate (FER) performance with very low message precision. For message-passing according to a flooding schedule, the RCQ parameters are designed by discrete density evolution. Simulation results on an IEEE 802.11 LDPC code show that for 4-bit messages, a flooding Min Sum RCQ decoder outperforms table-lookup approaches such as information bottleneck (IB) or Min-IB decoding, with significantly fewer parameters to be stored. Additionally, this paper introduces layer-specific RCQ, an extension of RCQ decoding for layered architectures. Layer-specific RCQ uses layer-specific message representations to achieve the best possible FER performance. For layer-specific RCQ, this paper proposes using layered discrete density evolution featuring hierarchical dynamic quantization (HDQ) to design parameters efficiently. Finally, this paper studies field-programmable gate array (FPGA) implementations of RCQ decoders. Simulation results for a (9472, 8192) quasi-cyclic (QC) LDPC code show that a layered Min Sum RCQ decoder with 3-bit messages achieves more than a 10% reduction in LUTs and routed nets and more than a 6% decrease in register usage while maintaining comparable decoding performance, compared to a 5-bit offset Min Sum decoder.

The aim of our work is to realize the implementation of a real-time high-quality image rotation on FPGA's board. The method we used is based on M. Unser's work and consists in applying a B-spline interpolator. The difficulty of this problem is due to the relatively weak integration capacity of FPGAs. To solve this problem we have searched for determining the minimum number of bits to code the filter while keeping a good accuracy of filtering output. In this article, we remind a few definitions about B-spline functions and we present how we use B- spline interpolation for the image rotation problem. Then, we describe the way we calculate probability density function of the output error in order to determine the filter data coding.

Tree exploration with advice

In this paper, we propose a novel multihop transmission scheme using selective network coding (NC) and differential modulation (SNC-DM) for two-way relay networks (TWRNs) when neither the source nodes nor the relay nodes know the channel state information (CSI). We first develop a bidirectional transmission scheme using NC where the information exchange in a two-way multihop relay network with the arbitrary number of hops can be completed in four transmission phases. As a result, the maximum achievable throughput does not decrease as the number of hops increases. To overcome the error propagation in the multihop transmission with decode-and-forward (DF) protocol in wireless fading channels, a selective NC scheme is proposed. In addition, we apply differential modulation in the proposed scheme to avoid channel estimation in the multihop networks. The performance of the proposed scheme is analyzed, and a closed-form frame error rate (FER) expression is derived. It is shown that the proposed scheme achieves significant improvements in both FER performance and network throughput compared to the conventional multihop DF scheme in TWRNs. The analytical results are verified through numerical simulations.

We study the amount of knowledge about the network that is required in order to efficiently solve a task concerning this network. The impact of available information on the efficiency of solving network problems, such as communication or exploration, has been investigated before but assumptions concerned availability of particular items of information about the network, such as the size, the diameter, or a map of the network. In contrast, our approach is quantitative: we investigate the minimum number of bits of information (minimum oracle size) that has to be given to an algorithm in order to perform a task with given efficiency. We illustrate this quantitative approach to available knowledge by the task of tree exploration. A mobile entity (robot) has to traverse all edges of an unknown tree, using as few edge traversals as possible. The quality of an exploration algorithm ${\cal A}$ is measured by its competitive ratio, i.e., by comparing its cost (number of edge traversals) to the length of the shortest path containing all edges of the tree. Depth-First-Search has competitive ratio 2 and, in the absence of any information about the tree, no algorithm can beat this value. We determine the minimum number of bits of information that has to be given to an exploration algorithm in order to achieve competitive ratio strictly smaller than 2. Our main result establishes an exact threshold oracle size that turns out to be roughly loglogD, where D is the diameter of the tree. More precisely, for any constant c, we construct an exploration algorithm with competitive ratio smaller than 2, using an oracle of size at most loglogD –c, and we show that every algorithm using an oracle of size loglogD –g(D), for any function g unbounded from above, has competitive ratio at least 2.

Channel coding is a fundamental procedure in wireless telecommunication systems and has a strong impact on the data transmission quality. This effect becomes more important when the transmission must be characterised by low latency and low bit error rate, as in the case of vehicle-to-everything (V2X) services. Thus, V2X services must use powerful and efficient coding schemes. In this paper, we thoroughly examine the performance of the most important channel coding schemes in V2X services. More specifically, the impact of use of 4th-Generation Long-Term Evolution (4G-LTE) turbo codes, 5th-Generation New Radio (5G-NR) polar codes and low-density parity-check codes (LDPC) in V2X communication systems is researched. For this purpose, we employ stochastic propagation models that simulate the cases of line of sight (LOS), non-line of sight (NLOS) and line of sight with vehicle blockage (NLOSv) communication. Different communication scenarios are investigated in urban and highway environments using the 3rd-Generation Partnership Project (3GPP) parameters for the stochastic models. Based on these propagation models, we investigate the performance of the communication channels in terms of bit error rate (BER) and frame error rate (FER) performance for different levels of signal to noise ratio (SNR) for all the aforementioned coding schemes and three small V2X-compatible data frames. Our analysis shows that turbo-based coding schemes have superior BER and FER performance than 5G coding schemes for the vast majority of the considered simulation scenarios. This fact, combined with the low-complexity requirements of turbo schemes for small data frames, makes them more suitable for small-frame 5G V2X services.

Polar codes are the first provably capacity-achieving forward error correction codes. To improve decoder throughput, the symbol-decision SC algorithm makes hard-decision for multiple bits at a time. In this paper, we prove that for polar codes, the symbol-decision SC algorithm is better than the bit-decision SC algorithm in terms of the frame error rate (FER) performance because the symbol-decision SC algorithm performs a local maximum likelihood decoding within a symbol. Moreover, the bigger the symbol size, the better the FER performance. Finally, simulation results over both the additive white Gaussian noise channel and the binary erasure channel confirm our theoretical analysis.

The potential gains of multiple antennas in wireless systems can be limited by channel state information imperfections. In this context, this paper tackles the limited feedback in multiuser correlated multiple input single output (MU-MISO). We propose a framework to feedback the minimum number of bits with limited performance degradation. This framework is based on decor relating the channel state information by compression and then quantize the compressed (CSI) and feedback it to the base station (BS). We characterize the rate loIEEss resulting from the proposed framework. An upper bound on the rate loss is derived in terms of the amount of feedback and the statistics of the channel. Based on this characterization, we propose an adaptive bit allocation algorithm that takes into the account the channel statistics to reduce the rate loss induced by the quantization. Moreover, in order to maintain a constant rate loss with respect to perfect CSI, it is shown that the number of feedback bits should scale linearly with the SNR (in dB) and to the rank of the user transmit correlation matrix. We validate the proposed framework by Monte-carlo simulations.

This brief presents a nonbinary adaptive 2D scheduling-based majority logic decoding (NB-ATS-MLGD) algorithm for NAND flash memory. The proposed algorithms provide considerable tradeoff between error-correcting capability and decoding complexity, and make the NB-MLGD decoding more attractive for practical purposes in the multi-level cells (MLC) NAND flash memory. The most significant feature of the proposed NB-ATS-MLGD algorithm is the 2D layered scheduling strategy, where the decoding orders of check nodes (CNs) and variable nodes (VNs) are both adaptive. By leveraging on the MLC flash memory bit error patterns, an early-correcting (EC) criterion is incorporated into the NB-ATS-MLGD algorithm. Furthermore, the simplification and parallelization of proposed algorithms make them more practical in NAND flash memory. Simulation results show that the proposed algorithms increase the lifetime of MLC flash memory up to 3000 program-and-erase (PE) cycles and have desirable convergence speed compared with the conventional non-binary MLGD algorithm. When at low PE cycles, the NB-EC-ATS-MLGD algorithm improves frame error rate (FER) performance by more than 3 order of magnitudes compared with the conventional non-binary MLGD algorithm.

Fast radio broadcasting with advice

In this paper an implementation of the Inverse Numerical Laplace Transform (INLT) on a Field Programmable Gate Array (FPGA) is presented. A brief description of INLT algorithms based on FFT are made and its MATLAB implementation is performed in order to have a comparison basis with FPGA results. A fixed point representation is used and it is optimized using fi MATLAB object. INLT is basically composed by three stages: Windowing, FFT and exponential function multiplications, the last stage is considered the critical one because it can result in severely large errors, specially, when several samples are required. Errors can be reduced by increasing the number of bits, however this increment makes the required FPGA area greater. Windowing and FFT can be implemented with high accuracy on FPGA with CORDIC and Cooley Tukey algorithms respectively, making the implementation flexible. The implementation was made with Verilog description hardware language using Xilinx technology and Virtex 6 FPGA.

The intra-cell characteristics of TLC NAND Flash memory are analyzed based on the channel model employed in this paper. In order to solve the read latency and the reliability degradation, caused by LDPC soft decision decoding and by the increase of flash storage density, respectively, a dynamic block grouping approach is proposed to divide all variable nodes (VNs) into three sub-blocks. To exploit the reliability of the VNs within the three sub-blocks, different update operations are performed in order. Moreover, the decoding latency is reduced with fewer iterations for the VNs in the most reliable sub-block, at the same time, the priority for updating of the reliable sub-block and the timely processing of the VNs with low-information have more useful information transmitted in the iterative decoding process, resulting in the improved convergency speed. In quantity, our simulation results show that the proposed algorithm improves the convergency rate by about 28.6% and reduces the average number of iterations by around 27.7%, compared with the VNBP-MP algorithm without compromising the error correction performance on the TLC NAND Flash devices.

The implementation of data acquisition and real-time backprojection via a bit-slice microprocessor system places serious constraints on data format in TOF-PET systems. To minimize hardware costs and complexity and enhance processing speed, internal data representation is to be realized with a minimum number of bits without significant loss of accuracy. Specifically, we have examined in detail data formats necessary for the quantization of the TOF data and reconstruction filtering via integer FFT's. Estimates of data degradation as related to number of bits utilized have been obtained. It is shown that a significant reduction in image memory size and improvement in speed of computation can be achieved with the appropriate choice of data formats and algorithms.

With the recent trend of promoting Field-Programmable Gate Arrays (FPGAs) to first-class citizens in accelerating compute-intensive applications in networking, cloud services and artificial intelligence, FPGAs face two major challenges in sustaining competitive advantages in performance and energy efficiency for diverse cloud workloads: 1) limited configuration capability for supporting light-weight computations/on-chip data storage to accelerate emerging search-/data-intensive applications. 2) lack of architectural support to hide reconfiguration overhead for assisting virtualization in a cloud computing environment. In this paper, we propose a reconfigurable memory-oriented computing fabric, namely Liquid Silicon-Monona (L-Si), enabled by emerging nonvolatile memory technology i.e. RRAM, to address these two challenges. Specifically, L-Si addresses the first challenge by virtue of a new architecture comprising a 2D array of physically identical but functionally-configurable building blocks. It, for the first time, extends the configuration capabilities of existing FPGAs from computation to the whole spectrum ranging from computation to data storage. It allows users to better customize hardware by flexibly partitioning hardware resources between computation and memory, greatly benefiting emerging search- and data-intensive applications. To address the second challenge, L-Si provides scalable multi-context architectural support to minimize reconfiguration overhead for assisting virtualization. In addition, we provide compiler support to facilitate the programming of applications written in high-level programming languages (e.g. OpenCL) and frameworks (e.g. TensorFlow, MapReduce) while fully exploiting the unique architectural capability of L-Si. Our evaluation results show L-Si achieves 99.6% area reduction, 1.43× throughput improvement and 94.0% power reduction on search-intensive benchmarks, as compared with the FPGA baseline. For neural network benchmarks, on average, L-Si achieves 52.3× speedup, 113.9× energy reduction and 81% area reduction over the FPGA baseline. In addition, the multi-context architecture of L-Si reduces the context switching time to - 10ns, compared with an off-the-shelf FPGA (∼100ms), greatly facilitating virtualization.

An efficient AES implementation using FPGA with enhanced security features