Hardware Trojan Attacks: Threat Analysis and Countermeasures

Here, the side-channel attack (SCA)-resistant cryptographic chip: a cryptographic circuit employs a voltage scaling technique is studied with hardware Trojan attacks. Two different types of hardware Trojans, sequential hardware Trojan and combinational hardware Trojan, are proposed to be embedded into the SCA-resistant cryptographic chip for leaking the secret key. Moreover, the sequential Trojan can only disclose a single bit of the secret key at a time, while the combinational Trojan is able to leak the whole bit of the secret key at once. As demonstrated in the results, only analysing ∼270 (150) power traces are sufficient to disclose the 8-bit secret key of the sequential (combinational) Trojan-infected chip to the adversary. Furthermore, both the sequential and combinational Trojan-infected chips can evade the testing of the power attack and be detected with the proposed statistical models successfully.

ABSTRACTThe tremendous advancement in very large scale integration technology encourages chip designers to rely on commercial electronic design automation tools, offshore fabrication services, and outsourced intellectual property cores. As third-party involvement are more in chip design cycle, integrated circuits (IC) such as programmable logic devices (PLD) and application specific ICs (ASIC) are highly vulnerable to hardware Trojan (HT) attacks. HTs are malicious additions or modifications to existing circuit elements, which can be inserted at any stages of IC life cycle to modify/destroy the functionality, reduce reliability, leak sensitive information, etc. Besides, HT can be designed either as always on or triggered only under certain operating conditions. For example, HT attacks in safety critical applications such as nuclear power plant, space and defence will jeopardise the safety and security of the unit and cause serious consequences. Hence, it is most important to ensure that the chip being in use performs only the intended function. In this paper, an in-depth analysis of feasible HT attacks in PLD and ASIC life cycles are presented. Based on the extensive literature survey on HTs and their countermeasure techniques, the state of the art HT prevention, detection, and diagnosis techniques are recommended to the valid stages of PLD and ASIC life cycles. Therefore, incorporating possible HT defence solutions in respective phases of PLD/ASIC-based safety systems thwart them against HT attacks.

Hardware Trojan detection via rewriting logic

Due to the nature of the industrial control systems (ICS) environment, where process continuity is essential, intentionally initiating a cyberattack to check security controls can cause severe financial and human damage to the organization. Therefore, most organizations operating ICS environments check their level of security through simulated cybersecurity exercises. For these exercises to be effective, high-quality cyberattack scenarios that are likely to occur in the ICS environment must be assumed. Unfortunately, many organizations use limited attack scenarios targeting essential digital assets, leading to ineffective response preparedness. To derive high-quality scenarios, there is a need for relevant attack and vulnerability information, and standardized methods for creating and evaluating attack scenarios in the ICS context. To meet these challenges, we propose GENICS, an attack scenario generation framework for cybersecurity training in ICS. GENICS consists of five phases: threat analysis, attack information identification, modeling cyberattack scenarios, quantifying cyberattacks, and generating scenarios. The validity of GENICS was verified through a qualitative study and case studies on current attack scenario-generating methods. GENICS ensures a systematic approach to generate quantified, realistic attack scenarios, thereby significantly enhancing cybersecurity training in ICS environments.

Logic locking has been proposed as an obfuscation technique to protect outsourced IC designs from IP piracy by untrusted entities in the design and fabrication process. In this case, the netlist is locked by adding extra key-gates, and will be unlocked only if a correct key is applied to the key-gates. The key is assumed to be written into a non-volatile memory after the fabrication by the IP owner. In the past several years, the focus of the research community has been mostly on Oracle-guided attacks, such as SAT attacks, on logic locking and proposing proper countermeasures against such attacks. However, none of the reported research in the literature has ever challenged a more fundamental assumption of logic locking, which is the security of the key itself. In other words, if an adversary can read out the correct key after insertion, the security of the entire scheme is broken. In this work, we first review possible adversaries for the locked circuits and their capabilities. Afterward, we demonstrate that even with the assumption of having a tamper- and read-proof memory for the key storage, which is not vulnerable to any physical attacks, the key transfer between the memory and the key-gates through registers and buffers make the key extraction by an adversary possible. To support our claim, we implemented a proof-of-concept locked circuit as well as one of the standard logic locking benchmarks on an FPGA manufactured with a 28 nm technology and extract obfuscation keys using optical probing. Finally, we discuss the feasibility of the proposed attack in different scenarios and propose potential countermeasures.

Malicious hardware modification, also known as hardware Trojan attack, has emerged as a serious security concern for electronic systems. Such attacks compromise the basic premise of hardware root of trust. Over the past decade, significant research efforts have been directed to carefully analyze the trust issues arising from hardware Trojans and to protect against them. This vast body of work often needs to rely on well-defined set of trust benchmarks that can reliably evaluate the effectiveness of the protection methods. In recent past, efforts have been made to develop a benchmark suite to analyze the effectiveness of pre-silicon Trojan detection and prevention methodologies. However, there are only a limited number of Trojan inserted benchmarks available. Moreover, there is an inherent bias as the researcher is aware of Trojan properties such as location and trigger condition since the current benchmarks are static. In order to create an unbiased and robust benchmark suite to evaluate the effectiveness of any protection technique, we have developed a comprehensive framework of automatic hardware Trojan insertion. Given a netlist, the framework will automatically generate a design with single or multiple Trojan instances based user-specified Trojan properties. It allows a wide variety of configurations, such as the type of Trojan, Trojan activation probability, number of triggers, and choice of payload. The tool ensures that the inserted Trojan is a valid one and allow for provisions to optimize the Trojan footprint (area and switching). Experiments demonstrate that a state-of-the-art Trojan detection technique provides poor efficacy when using benchmarks generated by our tool. This tool is available for download from http://www.trust-hub.org/.

Hardware Trojan detection techniques have been studied extensively. However, to develop reliable and effective defenses, it is important to figure out how hardware Trojans are implemented in practical scenarios. The authors attempt to make a review of the hardware Trojan design and implementations in the last decade and also provide an outlook. Unlike all previous surveys that discuss Trojans from the defender's perspective, for the first time, the authors study the Trojans from the attacker's perspective, focusing on the attacker's methods, capabilities, and challenges when the attacker designs and implements a hardware Trojan. First, the authors present adversarial models in terms of the adversary's methods, adversary's capabilities, and adversary's challenges in seven practical hardware Trojan implementation scenarios: in‐house design team attacks, third‐party intellectual property vendor attacks, computer‐aided design tools attacks, fabrication stage attacks, testing stage attacks, distribution stage attacks, and field‐programmable gate array Trojan attacks. Second, the authors analyse the hardware Trojan implementation methods under each adversarial model in terms of seven aspects/metrics: hardware Trojan attack scenarios, the attacker's motivation, feasibility, detectability (anti‐detection capability), protection and prevention suggestions for the designer, overhead analysis, and case studies of Trojan implementations. Finally, future directions on hardware Trojan attacks and defenses are also discussed.

Micromotor fabrication and related issues are discussed. The micromotors under study are of the variable-capacitance side-drive type with salient-pole and wobble (harmonic) designs. Polysilicon surface micromachining forms the basis of the micromotor fabrication process. In this process, LPCVD heavily phosphorus-doped polysilicon is used for the structural parts, LPCVD silicon nitride is used for electrical isolation, and CVD low-temperature oxide is used to as the sacrificial material. The fabrication process affects the performance characteristics of the micromotor through the reproduction accuracy of the design geometry and through the modification of the characteristics of contacting surfaces. Pattern definition and delineation are among the most critical steps of the micromotor fabrication process because of the increasing surface topography during fabrication and the large film thicknesses utilized. The release and testing process can affect the frictional characteristics of the micromotor significantly, determining success or failure of operation by dielectric excitation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This study addresses a critical deficiency in real estate management by examining how contractual arrangements between property owners and facility managers (FMs) can mitigate reputational damage arising from third-party liability incidents. While Spanish regulations impose comprehensive conservation and maintenance duties on property owners, current contractual frameworks inadequately protect owners from reputational risks when damages occur due to FMs’ negligence or operational failures. This conceptual study employs a systematic analysis of 16 Spanish regulations governing real estate conservation and maintenance duties, complemented by an examination of the statutory contract law and a Strengths, Weaknesses, Opportunities, and Threats (SWOT) analysis to evaluate the proposed solutions. The analysis reveals four distinct liability attribution blocks, ranging from quasi-objective owner liability to full objective installation holder liability. Current service contracts between owners and FMs provide insufficient reputational protection, as civil liability remains with the property owners regardless of the FMs’ performance. This study identifies specific contractual mechanisms—combining statutory work contracts with representative mandates and installation ownership transfers—that effectively redirect tort liability from owners to FMs. While this study focuses on Spanish regulatory frameworks as a methodologically necessary foundation for theoretical development, the conceptual framework provides transferable mechanisms for adaptation to other civil law jurisdictions. This study constitutes the first comprehensive analysis bridging legal architecture and facility management to propose novel liability transfer mechanisms within established frameworks.

Threat Analysis and Attacks on XtreemOS: a Grid–enabled Operating System

Communication towers are essential infrastructure in modern society, require effective life cycle cost (LCC) control for long-term sustainability. While existing research has focused on structural optimization and technological advancements, few studies address cost-related issues across various stages, perspectives, and stakeholders. A multi-source factor identification approach was employed, combining literature review, field surveys, expert interviews, brainstorming, and questionnaires. An integrated Grey-SNA-ISM model was then developed. The method identified 49 factors influencing LCC, integrated Grey-SNA centrality indicators, and established four network hierarchies, which include source-driven, intermediary conduction, collaborative central control, and outcome response. A nine-layer causal hierarchy categorizes factors into fundamental, transitional, and direct influences, revealing a multi-level transmission path from institutional drivers to execution feedback. The results indicate that inadequate policy standards, insufficient management experience, and environmental constraints serve as top-level drivers. These factors flow through intermediary stages like procurement errors and design deviations, leading to downstream cost risks, such as construction delays and operational failures. This creates a dynamic, three-tier cascading structure at the strategic, organizational, and execution levels. The integrated model proposed demonstrates significant adaptability in LCC modeling for communication towers, offering methodological support for factor classification and path identification. Additionally, it shows potential for application in other complex cost systems, facilitating precise interventions and cost control throughout the life cycle.

This paper introduces the relevant content of LXI bus technology including its developments, classification, and research status of synchronous triggering of LXI bus. Based on the discussion of hardware triggering techniques, a feasible structure of LXI class A instrument is proposed. Its hardware and software design is described in detail. In hardware design, the M-LVDS drivers are adopted to complete the transmission of triggering events and satisfy the specification of LXI class A instruments. Because of the high performance cast ratio, ARM processor is adopted to be the controller of the instrument. The software scheme is also proposed. The instrument software is designed as a Web server. With a browser, users can access LXI instruments through communicating with IVI-COM drivers. The proposed instrument scheme has the advantages of wider coverage, better succession, longer life cycle, lower cost, greater data throughput and so on.

Miniaturization and utilization of low-dimensional structures of recent electronic devices have witnessed some new micro cooling methods which can fulfil the cooling demand for the electronic devices. Microchannel heat sink (MCHS) is one of the micro cooling method which appears as a promising method that can provide high heat transfer rate due to small hydraulic diameter. Furthermore, microchannel heat sink is easy to be fabricated compare to other micro cooling device. Due to fast development in electronic industry, hybrid microchannel heat sink with optimal design has received a great deal of attention in order to provide sustainable cooling solutions. However, most of the studies of hybrid microchannel heat sink only provided the numerical analysis without any validation of the proposed design experimentally. This is very important since it also will determine whether the proposed hybrid microchannel heat sink can be fabricated or not. Therefore, the aim of this article is to validate the numerical model of hybrid microchannel heat sink (TC-RR-SC MCHS) experimentally. The validation result showed that the maximum discrepancy between both simulation and experimental analyses for Nusselt number and friction factor were 15.8% and 17.4%, respectively, which is less than 20%. The different number of microchannels between the simulated TC-RR-SC MCHS and fabricated TC-RR-SC MCHS is one of the factors that contribute to the data discrepancy. Furthermore, the poor finishing during the fabrication process also another factor because the burrs and debris at the top and bottom surface of microchannels affect the convective heat transfer area and the flow area of fluid.

Deviated well sections are common in modern well construction. In mature areas like the North Sea region, practically all producers or injector wells will have highly deviated sections. These wells must be completed in an optimal manner including annular barrier integrity. This is important for zonal isolation through all stages of the well’s life cycle. Since all wells must be permanently plugged before abandonment it is important to ensure that annular barriers are designed with a long term perspective and not only to minimize construction time and cost. Controlled laboratory environments with various fluid compositions and flow parameters are important to develop, validate and improve models and practices. Cement displacement is normally the objective for such studies. Due to selection of fluids, data for casing cleaning operations are in reality derived. Fundamental flow properties are investigated qualitatively. Water with and without viscosifiers is used to displace similar fluids from the annular section. The effects of inner pipe rotation are included. It is shown how this gives fundamental data providing a relevant background for understanding displacement processes. The experiments have been performed in a flow loop that consists of a 10 meters long test section with 5″ OD transparent pipe inside a 6,5″ transparent pipe. Experiments were performed with concentric and eccentric horizontal annulus and both with rotating and non-rotating inner pipe. The applied flow loop dimensions are designed so that the results should be relevant for highly inclined sections in field operation.

The goal of this study is to estimate the county-level environmental performance for continuous corn cultivation of corn grain and corn stover grown under the current tillage practices for various corn-growing locations in the US Corn Belt. The environmental performance of corn grain varies with its farming location because of climate, soil properties, cropping management, etc. Corn stover, all of the above ground parts of the corn plant except the grain, would be used as a feedstock for cellulosic ethanol. Two cropping systems are under investigation: corn produced for grain only without collecting corn stover (referred to as CRN) and corn produced for grain and stover harvest (referred to as CSR). The functional unit in this study is defined as dry biomass, and the reference flow is 1 kg of dry biomass. The system boundary includes processes from cradle to farm gate. The default allocation procedure between corn grain and stover in the CSR system is the system expansion approach. County-level soil organic carbon dynamics, nitrate losses due to leaching, and nitrogen oxide and nitrous oxide emissions are simulated by the DAYCENT model. Life cycle environmental impact categories considered in this study are total fossil energy use, climate change (referred to as greenhouse gas emissions), acidification, and eutrophication. Sensitivities on farming practices and allocation are included. Simulations from the DAYCENT model predict that removing corn stover from soil could decrease nitrogen-related emissions from soil (i.e., N2O, NO x , and NO3 − leaching). DAYCENT also predicts a reduction in the annual accumulation rates of soil organic carbon (SOC) with corn stover removal. Corn stover has a better environmental performance than corn grain according to all life cycle environmental impacts considered. This is due to lower consumption of agrochemicals and fuel used in the field operations and lower nitrogen-related emissions from the soil. The primary source of total fossil energy associated with biomass production is nitrogen fertilizer, accounting for over 30% of the total fossil energy. Nitrogen-related emissions from soil (i.e., N2O, NO x , and NO3 − leaching) are the primary contributors to all other life cycle environmental impacts considered in this study. The environmental performance of corn grain and corn stover varies with the farming location due to crop management, soil properties, and climate conditions. Several general trends were identified from this study. Corn stover has a lower impact than corn grain in terms of total fossil energy, greenhouse gas emissions, acidification, and eutrophication. Harvesting corn stover reduces nitrogen-related emissions from the soil (i.e., N2O, NO x , NO3 −). The accumulation rate of soil organic carbon is reduced when corn stover is removed, and in some cases, the soil organic carbon level decreases. Harvesting only the cob portion of the stover would reduce the negative impact of stover removal on soil organic carbon sequestration rate while still bringing the benefit of lower nitrogen-related emissions from the soil. No-tillage practices offer higher accumulation rates of soil organic carbon, lower fuel consumption, and lower nitrogen emissions from the soil than the current or conventional tillage practices. Planting winter cover crops could be a way to reduce nitrogen losses from soil and to increase soil organic carbon levels. County-level modeling is more accurate in estimating the local environmental burdens associated with biomass production than national- or regional-level modeling. When possible, site-specific experimental information on soil carbon and nitrogen dynamics should be obtained to reflect the system more accurately. The allocation approach between corn grain and stover significantly affects the environmental performance of each. The preferred allocation method is the system expansion approach where incremental fuel usage, additional nutrients in the subsequent growing season, and changes in soil carbon and nitrogen dynamics due to removing corn stover are assigned to only the collected corn stover.