Heterostructure Ge-Body pTFETs for Analog/RF Applications

Radio-frequency modeling of square-shaped extended source tunneling field-effect transistors

Hexagonal boron nitride encapsulation significantly improves carrier transport in graphene. This paper investigates the benefit of implementing the encapsulation technique in graphene field-effect transistors (GFETs) in terms of their intrinsic radio frequency (RF) performance, adding the effect of the series resistances at the terminals. For such a purpose, a drift-diffusion self-consistent simulator is prepared to get the GFET electrical characteristics. Both the mobility and saturation velocity are obtained by an ensemble Monte Carlo simulator upon considering the relevant scattering mechanisms that affect carrier transport. RF figures of merit are simulated using an accurate small-signal model. Results reveal that the cutoff frequency could scale up to the physical limit given by the inverse of the transit time. Projected maximum oscillation frequencies, in the order of few terahertz, are expected to exceed the values demonstrated by InP and Si-based RF transistors. The existing tradeoff between power gain and stability and the role played by the gate resistance are also studied. High power gain and stability are feasible even if the device is operated far away from current saturation. Finally, the benefits of device unilateralization and the exploitation of the negative differential resistance region to get negative-resistance gain are discussed.

Tunnel field effect transistors (TFETs) have proved their potential for many possible electronic circuit applications. However, with the variety of TFET structures being worked upon it has been an unresolved challenge to optimize them for the applications to which they are best suited. In this paper we present a detailed comparative analysis of the linearity distortion and the radiofrequency (RF) performance parameters of a proposed heterojunction Mg2Si source double gate TFET (HMSDG-TFET) and a conventional homojunction Si source DG-TFET (SSDG-TFET). A source material engineering scheme is utilized to implement a staggered type 2 heterojunction at the source–channel junction by replacing the source material with Mg2Si (a low band gap material) to enhance the ON current (2.5 × 10–4 A µm−1), reduce the threshold voltage (0.26 V) and achieve a steeper subthreshold swing (10.05 mV decade−1). For linearity and distortion analysis, the figure of merit (FOM)-like higher-order transconductances, second- and third-order voltage intercepts, third-order intercept point, third-order intermodulation distortion, zero crossover point, 1 dB compression point, second-order harmonic distortion, third order harmonic distortion and total harmonic distortion have been examined. To portray the possible application of devices under consideration for RF integrated circuit applications, both structures are investigated for RF FOMs such as power gains, cutoff frequency (fT), maximum oscillation frequency (F max) and admittance parameters. Investigations carried out using a Silvaco ATLAS device simulator tool revealed that with fT approximately three orders higher (0.49 THz) and F max approximately two orders higher (0.9 THz) than that of a SSDG-TFET, the HMSDG-TFET is an appropriate candidate for use in high-frequency, high-linearity, low-distortion and low-power analog/RF applications.

This paper reports the radio frequency (RF) and linearity performance of transistors using high-purity semiconducting carbon nanotubes. High-density, uniform semiconducting nanotube networks are deposited at wafer scale using our APTES-assisted nanotube deposition technique, and RF transistors with channel lengths down to 500 nm are fabricated. We report on transistors exhibiting a cutoff frequency (f(t)) of 5 GHz and with maximum oscillation frequency (f(max)) of 1.5 GHz. Besides the cutoff frequency, the other important figure of merit for the RF transistors is the device linearity. For the first time, we report carbon nanotube RF transistor linearity metrics up to 1 GHz. Without the use of active probes to provide the high impedance termination, the measurement bandwidth is therefore not limited, and the linearity measurements can be conducted at the frequencies where the transistors are intended to be operating. We conclude that semiconducting nanotube-based transistors are potentially promising building blocks for highly linear RF electronics and circuit applications.

This paper presents the results of extensive simulations on the characterization of asymmetrical channel device, namely Dual material Gate Fully Depleted Silicon On Insulator (DMG-FD-SOI) in the sub-100nm dimensions with emphasis on the analog, radio frequency (RF) performances and short channel effects (SCEs). The obtained results may serve as useful guidelines to get a basis overview of this gate-material engineered architecture. Improvement on cut-off, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">int</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and maximum oscillation frequency, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">int</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> are observed with the applied DMG design. Better SCEs and analog performances which are open loop gain (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ) and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio can be achieved with reduced silicon thickness, T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">si</sub> but with drawback on degraded <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">int</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">int</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> . For shorter gate length design of DMG in sub-100 nm dimension, higher threshold voltage, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> can be applied for SCEs suppression with insignificant degradation on the analog and RF point of views.

The effects of various notch structures on direct current (DC) and radio frequency (RF) performances of AlGaN/GaN high electron mobility transistors (HEMTs) are analyzed. The AlGaN/GaN HEMTs, each with a 0.8-μm gate length, 50-μm gate width, and 3-μm source–drain distance in various notch structures at the AlGaN/GaN barrier layer, are manufactured to achieve the desired DC and RF characteristics. The maximum drain current (I ds,max), pinch-off voltage (V th), maximum transconductance (g m), gate voltage swing (GVS), subthreshold current, gate leakage current, pulsed I–V characteristics, breakdown voltage, cut-off frequency (f T), and maximum oscillation frequency (f max) are investigated. The results show that the double-notch structure HEMT has a 30% improvement of gate voltage swing, a 42.2% improvement of breakdown voltage, and a 9% improvement of cut-off frequency compared with the conventional HEMT. The notch structure also has a good suppression of the current collapse.

Temperature sensitivity analysis of inner-gate engineered JL-SiNT-FET: An Analog/RF prospective

Effect of FIBL in-conjunction with channel parameters on analog and RF FOM of FinFET

The radio-frequency (RF) performance of a 0.18-/spl mu/m CMOS logic technology is assessed by evaluating the cutoff and maximum oscillation frequencies (f/sub T/ and f/sub max/), the minimum noise figure (F/sub min/) and associated power gain (G/sub a/), and the 1/f noise of the devices. Gate-biasing and channel-length and gate-finger-length adjustments are identified as means to optimize the RF performance without any technology process modifications. Changing to N/sub 2/O gate dielectrics is shown to greatly reduce the 1/f noise without sacrificing the AC performance. The power amplifier characteristics of CMOS at low power levels are also discussed.

Staggered heterostructure gate stack TFET is proposed. The analog, RF, and linearity performance of the device were studied in an ATLAS TCAD device simulator. The high K material HfO2 was used in gate stacking. The impact of the gate stack width on the analog, RF, and linearity performance was investigated. Analog/RF performance of the staggered heterostructure gate stack TFET were analyzed in terms of figure of merits (FOMs) like transconductance (gm), transconductance generation factor (TGF), voltage gain, electric field, cut off frequency (fT), maximum frequency of oscillation (fmax), and gain band width (GBW). Gate stacking architecture in heterostructure staggered TFET improves the Ion/Ioff ratio and reduces drain induced barrier lowering with respect to greater gate stack width (toxh), diminishing the short channel effects. Improvement in gm voltage gain, fT, fmax, and GBW) were observed as the gate stack width thickened. A fair comparison of FOMs such as VIP2, VIP3, IIP3, IMD3, and 1 dB–compression point (P1 dB) were carried out by varying the gate stack width to investigate the linearity performance. The simulation results reveal that staggered heterostructure gate stack TFET can be a reasonable competitor for low-power applications and in the design of RF circuits covering a wide range in frequencies of RF spectrum.

Analog and RF performance of a multigate FinFET at nano scale

This paper presents an electro-thermal radio frequency (RF) model and performance analysis for multilayer graphene nanoribbon (MLGNR) interconnects. The number of conduction channels is calculated as a function of temperature and Fermi energy. A comprehensive model is developed to calculate the temperature dependent effective mean free path (MFP) considering different scattering mechanisms. The RF model of doped and undoped metallic top-contact (TC), as well as side-contact (SC) MLGNR interconnects is demonstrated using ABCD parameter based multi-conductor transmission line formalism. The RF performance of arsenic pentafluoride ( $$\text {AsF}_5$$ ), lithium (Li) and ferric chloride ( $$\text {FeCl}_3$$ ) intercalation doped TC-MLGNR interconnects is investigated and compared with pristine (undoped) TC and SC-MLGNR interconnects for different temperatures. For the first time, our investigation shows that the electro-thermal RF performance of TC-MLGNR can be improved by intercalation doping. It is found that $$\text {AsF}_5$$ , Li and $$\text {FeCl}_3$$ intercalated top-contact MLGNR can operate up to a few GHz for semi-global interconnects ( $$100\,\upmu $$ m) and several MHz for global interconnects ( $$500\,\upmu $$ m). Our analysis also proves that the Li intercalated TC-MLGNR shows the best RF performance as compared to conventional copper, pristine, and other type of intercalation doped TC-MLGNR interconnects over the chip operating temperature range from 233 to 378 K. The performance of Li intercalated TC-MLGNR has been found to be improved further by increasing the specularity during fabrication.

Many times, the fabricated cylindrical gate-all-around tunnel FET (GAA TFET) has an uneven radius due to several etching and deposition processes involved while fabricating the device, which show notable variations in the performance of the device. In this report, III–V uneven GAA TFET is studied by considering the uneven radius as elliptical in shape for all possible variations, which shows a significant impact on analog and RF figure of merits (FOMs). The performance of the optimized devices is compared with their circular structure and with their maximum deviation in elliptical geometry for all possible variations in device channel and gate oxide. The variations in its device channel and gate oxide have shown a significant impact on the performance of the device. The analog and RF FOMs are studied, including the transconductance generation factor (gm/IDS), intrinsic gain (gmRO), capacitances (CGS, CGD), cut-off frequency (fT), and gate delay (τm).

In the work purposed, the behavior of JLTMCSG MOSFET has been investigated by incorporating Dual Metals and Single Metal Gate with respect to different device parameters. The conclusion derived from the investigation reveals that DIBL can be suppressed and transportation capability of carrier can be improved by combining the advantages of junction-less architecture, gate terminal with three different material, and Cylindrical Surrounding Gate. We explore the radio frequency (RF) performance for JLTMCSG MOSFET taking in to account various figure of merits (FOMs) such as cutoff frequency fT, C-V curve, current gain, unilateral power gain and the simulated results are compared with JLDMCSG MOSFET.

A small-signal radio-frequency (RF) parameters extraction model along with analog/RF and linearity distortion performance analysis are realized for virtually doped (VD) recessed source/drain dopingless junctionless transistor (Re S/D DLJLT) via 3-D device simulations. A simple and accurate RF non-quasi-static (NQS) model is developed to directly extract the extrinsic and intrinsic parasitic components through Y-parameters in OFF and ON-state respectively. Furthermore, direct comparison of DC, analog/RF, linearity figure of merits (FOMs), and Y-parameter extractions are made with recessed source/drain junction transistor (Re S/D JT) with identical threshold voltage (Vth) and device dimensions at GHz frequency range. Virtual doping, due to charge-plasma (CP) concept, provides N+ source/drain (S/D) regions by choosing a most convenient metal work function (WF = 3.9 eV; Hafnium) at S/D. Re S/D provides reduced series resistance without an increase in gate-drain Miller capacitance leading to improved drive current. In addition, the present device uses an intrinsic channel and does not require to be doped at S/D resulting in dopingless junctionless transistor (DLJLT). For both devices, gate length (L) is taken as 30 nm, which separated into control gate (L1) and screen gate (L2) and 3-D simulations are carried out by varying control to screen gate length ratios (CSLR) to obtain optimum results. Obtained results disclose that Re S/D DLJLT provides considerably improved performances in terms of DC, analog/RF, linearity, transient, and small-signal admittance parameters over Re S/D JT due to improved drive current and reduced short channel effects (SCEs). Accordingly, for high-performance RF applications, Re S/D DLJLT may be preferred over Re S/D JT due to significantly enhanced cut-off frequency (up to 0.399 THz) and maximum oscillation frequency (up to 1.226 THz).